Semiconductor Device Trench Isolation Soft-Error Mitigation
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Solution Overview
Problem
Semiconductor devices, particularly SRAMs, face challenges in soft-error tolerance due to neutron rays from cosmic radiation, which are difficult to shield against and increase in frequency with device integration, leading to data corruption and errors.
Innovation Solution
The semiconductor device incorporates inverter circuits with second- and first-conductivity-type transistors, where diffusion layers are divided by trench isolation regions, and a silicon-on-insulator substrate is used to reduce noise charge inflow and enhance soft-error tolerance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device integration is improved to increase functionality, then productivity and adaptability improve, but soft-error tolerance deteriorates due to increased susceptibility to neutron ray effects
Solution Approach 1:
The diffusion layers are divided into multiple regions by trench isolation regions, creating segmented structures that reduce the inflow of noise charges from radiation events while maintaining integrated device functionality
Solution Approach 2:
Trench isolation regions are introduced as intermediary structures between diffusion layers, acting as barriers that prevent noise charge propagation while allowing the device to maintain its integrated functionality
2Reliability
If trench isolation regions are introduced to reduce noise charge inflow, then soft-error tolerance improves, but device complexity increases
Solution Approach 1:
The diffusion layers are divided into multiple regions by trench isolation regions, creating segmented structures that reduce the inflow of noise charges from radiation events while maintaining integrated device functionality
Solution Approach 2:
Trench isolation regions create a porous or compartmentalized structure within the semiconductor device, allowing beneficial isolation of noise charges while maintaining overall device integrity and functionality
Data Source
AI summary
A second-conductivity-type transistor includes a source and drain formed by a second-conductivity-type diffusion layer formed on a first-conductivity-type semiconductor layer; and a gate formed on the first-conductivity-type semiconductor layer sandwiched between the second-conductivity-type diffusion layer through an insulating film A first-conductivity-type transistor includes a source and drain formed by a first-conductivity-type diffusion layer formed on a second-conductivity-type semiconductor layer; and a gate formed on the second-conductivity-type semiconductor layer sandwiched between the first-conductivity-type diffusion layer through an insulating film. The second-conductivity-type diffusion layer for configuring the second-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the first-conductivity-type semiconductor layer. The first-conductivity-type diffusion layer for configuring the first-conductivity-type transistor is divided into a plurality of regions, each of which being separated by a device isolation region formed on the second-conductivity-type semiconductor layer.