Semiconductor Trench Layout for High Withstand Voltage and Low On-Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor devices face challenges in achieving high withstand voltage while maintaining low on-resistance due to the limitations of existing guard ring trench structures, which often require separate outer peripheral structures that reduce the active region and affect performance.
Innovation Solution
The semiconductor device incorporates a layout with one or more outer peripheral trenches surrounding cell regions and an inter-cell distance smaller than the pitches of the cell trenches, allowing for a widened depletion layer and reduced on-resistance without separate outer peripheral structures, along with field plate trenches to alleviate electric field concentration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate outer peripheral structures are added to improve withstand voltage, then withstand voltage is improved, but device complexity and area loss increase
Solution Approach 1:
The patent merges the outer peripheral trench structure with the cell trench structure by making the outer peripheral trench share the same bottom wall as the cell trench. This integration eliminates the need for separate outer peripheral structures while maintaining the withstand voltage function, thereby reducing device complexity and area loss.
Solution Approach 2:
The outer peripheral trench is designed to serve multiple functions: it acts as a guard ring structure for withstanding voltage, provides mechanical support, and defines the device boundary. This multi-functionality eliminates the need for additional separate structures, reducing overall device complexity while maintaining reliability.
2Reliability
If guard ring trenches are added around elements to improve withstand voltage, then withstand voltage is improved, but active region area decreases
Solution Approach 1:
The patent merges the outer peripheral trench with the cell trench structure so that they share the same bottom wall. This integration allows the guard ring function to be achieved without occupying additional active region area, as the structure is formed within the existing trench footprint rather than as a separate surrounding structure.
Solution Approach 2:
The patent transitions from a planar guard ring structure to a vertical integration approach where the outer peripheral trench and cell trench share the same depth and bottom wall. This dimensional reorganization allows the withstand voltage function to be achieved in the vertical dimension rather than requiring additional horizontal space, thereby preserving active region area.
Data Source
AI summary
A semiconductor device includes: a semiconductor layer; cell trenches formed in the semiconductor layer; an insulating layer on the semiconductor layer; electrodes, each embedded in corresponding one of the cell trenches via the insulating layer; and one or more outer peripheral trenches formed in the semiconductor layer, wherein the cell trenches include: first set of cell trenches extending in first direction and arranged at first pitch in second direction; and second set of cell trenches extending in the second direction and arranged at second pitch in the first direction, wherein the semiconductor layer includes first and second cell regions where the first and second sets of cell trenches are arranged respectively, and the one or more peripheral trenches surround the first and second cell regions in a plan view, and wherein inter-cell distance between the first and second cell regions is smaller than both the first and second pitches.