Semiconductor Device Trench Termination for Leakage Control
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Solution Overview
Problem
The existing semiconductor devices require additional manufacturing steps for forming masks and etching to terminate the base and source layers, which increases manufacturing costs and complexity, and can lead to device breakdown due to leakage current and depletion layer extension.
Innovation Solution
A semiconductor device structure is developed where the p-type base layer and n+-type source layer are terminated by a second trench that penetrates through both layers, eliminating the need for extra lithography and etching steps, and includes a gate interconnect layer and channel stopper layer to manage the depletion layer and increase breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If masks are formed and etching is performed to terminate the base layer and source layer, then the depletion layer extension is prevented and device breakdown is avoided, but the manufacturing steps and complexity increase
Solution Approach 1:
The base layer and source layer are segmented into different regions (first region and second region) separated by a trench structure. This segmentation allows the depletion layer to be contained within the first region while the second region remains isolated, preventing depletion layer extension to the chip end portion without requiring complex mask patterns.
Solution Approach 2:
A trench structure filled with insulating film acts as an intermediary barrier between the first region containing the base and source layers and the chip end portion. This intermediary structure physically isolates the regions, preventing harmful electrical interactions and depletion layer extension while simplifying the manufacturing process by eliminating the need for additional mask formation steps.
2Device complexity
If the depletion layer extends to the chip end portion, then the device structure is simplified, but leakage current flows and device breakdown occurs
Solution Approach 1:
The trench filled with insulating film serves as an intermediary barrier that physically separates the active device region from the chip end portion. This intermediary structure prevents leakage current paths while maintaining a relatively simple overall device structure without requiring complex mask patterns or additional termination layers.
Solution Approach 2:
The harmful depletion layer extension and leakage current paths are extracted or removed from the active device region by introducing the trench structure. This extraction isolates the problematic electrical fields from the chip end portion, preventing breakdown while keeping the main device structure simple.
3Manufacturing precision
If extra mask formation steps are added to terminate the base and source layers, then the depletion layer is controlled, but the manufacturing cost increases
Solution Approach 1:
The device structure is segmented into distinct regions separated by a trench, allowing depletion layer control through geometric confinement rather than complex mask patterns. This segmentation achieves precise depletion layer management while using standard manufacturing processes, reducing overall manufacturing cost.
Solution Approach 2:
The control mechanism is changed from chemical mask deposition to physical geometric confinement using the trench structure. This parameter change in the control method eliminates the need for additional mask formation steps while maintaining precise depletion layer control, thereby reducing manufacturing complexity and cost.
Data Source
AI summary
In general, according to one embodiment, a semiconductor device includes a first electrode, a first and a second semiconductor layer of a first conductivity type, a third semiconductor layer of a second conductivity type, a fourth semiconductor layer of the first conductivity type in this order. A device region includes a gate electrode inside a first trench. A second trench having a ring-shaped structure forms a first region penetrating through the fourth and third semiconductor layers to the second semiconductor layer and including the device region inside and a second region surrounding the first region outside. A first opening is provided between adjacent ones of the first trenches. A second opening having a wider width than the first opening is provided in the first region outside the device region. A second electrode is electrically connected to the third and fourth semiconductor layers through the first and second openings.