Semiconductor Trench Structure for Leakage Reduction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As memory devices shrink in size, the increasing probability of short channel effects and random dopant fluctuations leads to challenges in maintaining accurate transistor operation and data retention due to gate-induced drain leakage and subthreshold leakage, which complicates the scaling of buried recessed access devices and requires frequent data refresh operations.
Innovation Solution
The formation of a semiconductor structure with deeper isolation trenches and varying depths of metallic and polysilicon materials in trenches to reduce charge transfer between adjacent transistors, allowing for reduced data refresh frequencies and improved data retention.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory devices are scaled down in size, then memory density increases, but short channel effects and random dopant fluctuations increase leading to gate-induced drain leakage and subthreshold leakage
Solution Approach 1:
The patent applies local quality by creating asymmetric trench depths - deeper isolation trenches in certain regions and shallower trenches in others - to provide different levels of charge transfer blocking where needed. This localized structural variation allows the memory device to maintain high density while selectively suppressing leakage in critical areas where short channel effects are most severe.
Solution Approach 2:
The patent transitions from two-dimensional planar transistor structures to three-dimensional structures with varying trench depths. By introducing depth as an additional dimension for charge transfer blocking, the patent achieves better leakage suppression without increasing lateral footprint, thereby maintaining high memory density while improving transistor reliability.
2Reliability
If deeper isolation trenches are formed to reduce charge transfer, then data retention improves, but manufacturing complexity increases
Solution Approach 1:
The patent segments the isolation trench formation into multiple depth levels - deeper trenches for critical isolation regions and shallower trenches for less critical areas. This segmentation allows the manufacturing process to target specific regions with appropriate trench depths, improving data retention in critical areas while avoiding the full manufacturing complexity of uniformly deep trenches across the entire device.
Solution Approach 2:
The patent applies partial action by forming trenches to different depths only where needed rather than uniformly across all regions. This selective approach achieves sufficient charge transfer blocking for data retention improvement while reducing the overall manufacturing complexity compared to forming all trenches to the maximum required depth.
3Object-generated harmful factors
If metallic material height is reduced in isolation trenches, then charge transfer between adjacent transistors decreases, but data refresh frequency requirements increase
Solution Approach 1:
The patent applies local quality by varying the metallic material height in different trench regions - reducing metallic material height in isolation trenches where charge transfer blocking is critical, while maintaining appropriate metallic material heights in active transistor regions. This localized variation effectively reduces charge transfer between adjacent transistors while preserving normal transistor operation and data refresh characteristics.
Data Source
AI summary
Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.