Semiconductor Trench Planarization via Auxiliary Layer Etching
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Solution Overview
Problem
Conventional semiconductor manufacturing processes, such as shallow trench isolation (STI), face challenges in achieving surface flatness due to dishing issues caused by non-uniform dielectric deposition and prolonged chemical mechanical polishing (CMP) processes, leading to inefficiencies and increased costs.
Innovation Solution
A method involving the formation of an auxiliary layer within trenches, followed by selective etching and additional dielectric deposition, allows for improved planarization processes that reduce dishing and enhance surface flatness without requiring complex photolithography or additional masks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the isolating dielectric is deposited to be rather thick to fill isolation trenches with adequate process margin for subsequent CMP, then the trenches can be adequately filled, but the CMP process must last for a long time and significant dishing occurs over wide isolation trenches
Solution Approach 1:
The patent applies preliminary action by depositing a first dielectric layer thicker than needed before CMP, then using a patterned removal layer to selectively remove dielectric material from specific regions (such as wide isolation trenches) before the CMP process. This preliminary selective removal prevents dishing in those regions during CMP, allowing the process to be completed in less time while maintaining surface flatness.
2Loss of time
If thicker isolating dielectric portions are exposed by patterned photoresist and thinned using dry etching to allow shortened CMP time, then CMP time is reduced, but the fabrication complexity and manufacturing cost increase
Solution Approach 1:
The patent uses an intermediary approach by introducing a removal layer made of a specific material (such as silicon nitride or silicon oxynitride) that has different etch selectivity compared to the dielectric layer. This removal layer acts as a mediator that can be selectively removed using wet etching or plasma etching processes, avoiding the need for complex photolithography and dry etching combinations. The removal layer is deposited conformally and then patterned, providing a simpler fabrication pathway while achieving the same goal of reducing CMP time.
3Manufacturing precision
If polish stop structures are added to wide isolation trenches to create multiple dense narrow trenches, then dishing is avoided, but additional masks are required increasing manufacturing cost
Solution Approach 1:
The patent applies local quality by making the removal layer thickness location-dependent. The removal layer is deposited conformally over the substrate, but its effective thickness varies in different regions due to the underlying topography and deposition conditions. In wide isolation trenches, the removal layer provides sufficient thickness for selective removal, while in narrow trenches, it maintains the necessary dielectric coverage. This spatial variation in removal layer properties enables selective dielectric removal in specific regions without requiring additional masks or complex patterning steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in improved surface flatness, reduced manufacturing costs, and shorter CMP times, addressing the inefficiencies and economic concerns of traditional methods by minimizing dishing and ensuring better semiconductor structure quality.
Implementation Method 1
etching back the auxiliary layer so that a top surface of the auxiliary layer is lower than a top surface of the first filling dielectric
Implementation Method 2
performing a first planarization process to remove a portion of the first filling dielectric until the auxiliary layer is exposed
Data Source
AI summary
A semiconductor structure and method for forming such a structure are disclosed by the present invention. In the method, before a first trench in a pre-processed substrate is filled with any filling material, an auxiliary layer is formed over an inner surface of the first trench. Afterward, a first filling dielectric is formed and an etch back process is performed so that a top surface of the first filling dielectric is higher than that of the pre-processed substrate, and a second filling dielectric is then formed and subject to a second planarization process.