Semiconductor Trench and Recess Planarization for Edge-Termination
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Solution Overview
Problem
The integration of chemical mechanical polishing (CMP) for planarization in semiconductor processing is challenging, especially when forming trench structures, as it removes all structures above the planarization level, leading to complex and costly processing flows, particularly when planarization reaches the main processing surface of the semiconductor workpiece.
Innovation Solution
A method involving forming trench structures and recesses in a semiconductor workpiece, depositing a material layer that fills these features, and then partially removing the layer through planarization, ensuring the material remains in the trenches and recesses, thereby simplifying the processing flow and reducing additional processing stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If chemical mechanical polishing (CMP) is used for planarization to reach the main processing surface, then surface flatness is improved, but processing complexity and cost increase
Solution Approach 1:
The patent applies preliminary action by forming recesses in regions where material will be removed during planarization, before the actual planarization process. This pre-positioning of material ensures that after CMP removes excess material to achieve the desired surface flatness, the recesses remain filled and provide the intended functionality without requiring additional processing steps.
Solution Approach 2:
The patent segments the semiconductor device into different regions with different depths - main regions at full depth and edge-termination regions with recesses at shallower depth. This segmentation allows the planarization process to achieve a single reference surface while preserving functional structures in both regions, reducing processing complexity.
2Manufacturing precision
If planarization removes all structures above the planarization level, then surface flatness is improved, but additional processing stages are required
Solution Approach 1:
The patent forms recesses in advance in the edge-termination regions before planarization. These recesses are filled with material that will remain after planarization removes excess material. This preliminary structuring eliminates the need for additional processing stages that would otherwise be required to create edge-termination structures after planarization.
Solution Approach 2:
The patent merges the formation of edge-termination structures with the planarization process itself. By pre-forming recesses and filling them with material, the edge-termination structures are created simultaneously with the planarization step, rather than requiring separate subsequent processing stages.
3Reliability
If trench structures are formed with deep etching, then device functionality is improved, but processing complexity increases
Solution Approach 1:
The patent applies local quality by creating regions with different depths - full-depth trenches in main regions for optimal device functionality, and shallower recesses in edge-termination regions. Each region has the appropriate depth and structure for its specific function, achieved through a single planarization process rather than multiple complex processing steps.
Solution Approach 2:
The patent uses preliminary action by pre-forming recesses in edge-termination regions before the planarization step. This allows deep trench structures to be created in main regions while simultaneously creating shallower structures in edge regions, both preserved through the planarization process without requiring additional processing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for the formation of polysilicon edge-termination field plates and gate resistors with reduced processing complexity, smaller size, improved variability, and lower costs, without additional topography or interlayer dielectric thinning, facilitating the integration of edge-termination structures and other functionalities.
Implementation Method 1
chemical mechanical polishing (CMP) process
Data Source
AI summary
A method for processing a semiconductor workpiece, including: forming a trench structure in a first region of a semiconductor workpiece, extending from a surface of the semiconductor workpiece to a first depth, forming at least one recess in a second region of the semiconductor workpiece laterally next to the first region, the recess extending from the surface of the semiconductor workpiece into the semiconductor workpiece to a second depth less than the first depth; forming a material layer over the semiconductor workpiece, the material layer filling the trench structure and recess and covering the surface of the semiconductor workpiece in the first region and in the second region; and planarizing the semiconductor workpiece to partially remove the material layer in the first region and in the second region, wherein the material layer remains in the trench structure and in the at least one recess.