Semiconductor Trench Patterning With Sidewall Spacer Etch Masks
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Solution Overview
Problem
As semiconductor device sizes continue to shrink, the critical dimension of the photolithography process approaches its physical limits, making it challenging to achieve desired patterns, and existing double-patterning techniques face limitations in improving device performance.
Innovation Solution
A method for forming semiconductor devices involves creating a to-be-etched layer with alternating first and second regions, forming mask layers, doping portions outside second trench regions, and using mask sidewall spacers and doped mask layers as etching masks to form second trenches, thereby improving pattern transfer and device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photolithography process is used, then manufacturing process is simple, but manufacturing precision deteriorates as critical dimension approaches physical limits
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages: first forming initial patterns, then using these patterns as templates to create additional patterns through epitaxial growth and selective removal. This multi-stage approach enables critical dimensions below the single photolithography limit while maintaining process control.
Solution Approach 2:
The patent employs preliminary action by pre-forming sacrificial patterns and epitaxial layers before final pattern definition. These preliminary structures serve as templates and masks for subsequent processing steps, enabling precise pattern transfer that overcomes photolithography resolution limits.
2Manufacturing precision
If double-patterning technique is used to overcome photolithography limits, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent transitions from two-dimensional planar patterning to three-dimensional vertical structuring through epitaxial growth. By growing vertical semiconductor layers with different compositions on the patterned substrate, the method creates additional pattern definition capability in the vertical dimension, enabling more complex patterns without proportionally increasing lateral process complexity.
Solution Approach 2:
The patent utilizes parameter changes by varying epitaxial growth conditions (temperature, pressure, gas flow, precursor ratios) to control the composition, thickness, and crystalline orientation of grown layers. These parameter adjustments enable precise control over pattern morphology and material properties, achieving high manufacturing precision while managing process complexity through controlled variable changes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enhances the control over the morphology of second trenches and improves the overall performance of semiconductor devices by reducing ion scattering and facilitating precise pattern formation beyond the limits of conventional photolithography.
Implementation Method 1
removing the first mask layer in the second trench regions by an etching process using the mask sidewall spacer and the doped portions of the first mask layer as an etching mask to form second trenches
Implementation Method 2
doping portions of the first mask layer outside second trench regions of the plurality of second regions
Implementation Method 3
forming a mask sidewall spacer on sidewall surfaces of the first trench in the first region of the plurality of first regions
Data Source
AI summary
Semiconductor device is provided. The semiconductor device includes a to-be-etched layer having a plurality of first regions and a plurality of second regions that are alternately arranged along a first direction, where the second region includes a second trench region; a first mask layer on the plurality of first regions and the plurality of second regions of the to-be-etched layer; a second mask layer on the first mask layer; a first trench penetrating the first mask layer and the second mask layer over a first region of the plurality of first regions; a mask sidewall spacer on sidewall surfaces of the first trench; and second trenches over the plurality of second trench regions of the plurality of second regions, where a sidewall surface of the second trench exposes a corresponding mask sidewall spacer of an adjacent first trench.