Tri-Layer Patterning for Semiconductor Line Width Uniformity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In semiconductor fabrication, the shrinking size of devices and reduced thickness/hardness of photoresist layers lead to challenges in controlling line width roughness and pattern size uniformity due to etching gas effects, resulting in non-uniform electrical properties across the substrate.
Innovation Solution
A method involving the formation of a hard mask layer, a patterned photoresist layer, and sidewall spacers is used to create patterns with substantially right angles, reducing etch bias loading and maintaining pattern size uniformity through a tri-layer patterning process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the thickness and hardness of the photoresist layer are reduced to match the shrinking minimum line width requirements, then the minimum line width can be reduced, but the line width roughness control becomes more difficult and the photoresist becomes more susceptible to etching gas effects
Solution Approach 1:
The patent divides the photoresist layer into multiple thinner sub-layers, each with controlled thickness. This segmentation allows the overall photoresist structure to maintain sufficient hardness and etching resistance while enabling the formation of smaller minimum line widths in each individual layer, thereby resolving the contradiction between reducing line width and maintaining manufacturing precision.
2Productivity
If the photoresist layer is exposed to etching gas during the etching process, then the etching process can proceed, but the photoresist near the top of openings becomes slanting and right angles become round angles
Solution Approach 1:
The patent applies a top coat layer to the photoresist pattern before the etching process. This preliminary action protects the photoresist pattern from direct exposure to etching gas, preventing the slanting and rounding effects that would otherwise occur during etching, while still allowing the etching process to proceed efficiently on the underlying layers.
Solution Approach 2:
The top coat layer serves as an intermediary between the etching gas and the photoresist pattern. It absorbs the harmful effects of the etching gas, preventing direct interaction with the photoresist, thereby maintaining the geometric integrity of the photoresist patterns while enabling the etching process to continue.
3Productivity
If the photoresist layer is partially removed during the etching process due to exposure to etching gas, then the etching can proceed, but the size of openings becomes greater than the designed size
Solution Approach 1:
The top coat layer is applied in advance before the etching process to provide protective coverage. This preliminary protective action prevents the photoresist from being partially removed during etching, ensuring that the opening sizes remain accurate and match the designed dimensions while still allowing complete etching process execution.
4Adaptability or versatility
If the device densities at different positions of the substrate are different, then various device configurations can be achieved, but the size of patterns formed by etching using photoresist with the same pattern size becomes different
Solution Approach 1:
The patent segments the photoresist structure into multiple layers with different thicknesses and properties. This multi-layer segmentation creates differential etching rates and protection levels across the structure, compensating for variations in device density at different substrate positions and maintaining uniform pattern sizes despite varying local device configurations.
Solution Approach 2:
The top coat layer provides localized protection that can be optimized for different regions of the substrate. By having a protective layer with specific properties, the system can maintain consistent pattern dimensions across areas with different device densities, as the local quality of the protective layer compensates for regional variations in etching conditions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes the size difference of patterns formed across the substrate, enhancing the uniformity and electrical properties of semiconductor devices by protecting the photoresist layer and maintaining vertical sidewalls during etching.
Implementation Method 1
forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist layer
Implementation Method 2
forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer
Data Source
AI summary
A method is provided for fabricating a semiconductor structure. The method includes providing a to-be-etched layer; and forming a hard mask layer on the to-be-etched layer. The method also includes forming a photoresist layer on the hard mask layer; and forming a patterned photoresist layer having openings exposing the hard mask layer by exposing and developing the photoresist layer. Further, the method includes forming sidewall spacers on side surfaces of the openings; and forming a patterned hard mask layer by etching the hard mask layer using the patterned photoresist layer and the sidewall spacers as an etching mask such that patterns in the hard mask layer have a substantially right angle at edge. Further, the method also includes forming to-be-etched patterns by etching the to-be-etched layer based on the patterned hard mask layer.