Semiconductor Device TSV Vertical Bit Line Interconnect
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Solution Overview
Problem
Existing semiconductor devices face limitations in increasing access speed due to restricted data length parallel access caused by wiring pitch on the flat surface of semiconductor chips.
Innovation Solution
A semiconductor device with a memory semiconductor chip and a planar buffer chip connected through a TSV (Through-Silicon Via) electrical connection structure, allowing bit lines to be connected in the thickness direction, and multiple bit wiring layers laminated on the planar buffer chip for parallel data access.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If bit lines are connected through surface wiring on a flat semiconductor chip, then the connection structure is simple, but the data length that can be accessed in parallel is restricted by wiring pitch
Solution Approach 1:
The patent transitions from two-dimensional surface wiring to three-dimensional vertical connections using TSVs (through-silicon vias). Bit lines are connected in the thickness direction of the chip, allowing multiple bit lines to be accessed in parallel without being constrained by surface wiring pitch. This dimensional change enables simultaneous access to a larger number of memory cells.
2Speed
If multiple bit lines are accessed in parallel, then access speed increases, but wiring pitch on flat surface restricts the number of bit lines
Solution Approach 1:
By utilizing the thickness direction (z-axis) for bit line connections through TSVs, the patent overcomes the lateral wiring pitch limitations. Multiple bit lines can be vertically stacked and connected to buffer circuits without increasing surface area, thereby enabling higher parallel access speeds.
Solution Approach 2:
The patent merges multiple bit lines from different memory semiconductor chips into a three-dimensional structure where they are vertically stacked and connected through TSVs to shared buffer circuits. This consolidation allows efficient parallel access to multiple bit lines while reducing the overall chip footprint.
3Productivity
If TSV electrical connection structure is used to connect bit lines in thickness direction, then parallel access capability increases, but manufacturing complexity increases
Solution Approach 1:
The patent implements TSVs to create vertical interconnections through the chip thickness, enabling multiple bit lines to be accessed in parallel. While TSV fabrication is more complex than planar wiring, it allows significantly higher parallel access capability by utilizing the third dimension for routing.
4Speed
If buffer circuits are provided for each bit line, then access speed increases, but chip area increases
Solution Approach 1:
The patent combines multiple bit lines from different memory chips into a three-dimensional stacked structure where they share common buffer circuits. This merging approach allows high-speed access to multiple bit lines while minimizing the required chip area by utilizing vertical stacking rather than lateral expansion.
Data Source
AI summary
This semiconductor device includes a memory semiconductor chip having a plurality of memory cells, a planar buffer chip which is a semiconductor chip that comprises a plurality of buffer circuits which hold data read from the memory cell and data written to the memory cell and which output the held data in accordance with the number of bit lines of the plurality of memory cells, an electrical connection structure which electrically connects the bit lines of the memory cells of the memory semiconductor chip and the buffer circuits of the planar buffer chip to each other in a thickness direction of the memory semiconductor chip and the planar buffer chip, and a plurality of bit wiring layers provided in accordance with the respective buffer circuits and electrically connected to the bit lines of the buffer circuits. The bit wiring layers are laminated on the planar buffer chip.