Semiconductor TSV Bonding Structure for Cost-Effective 3D Packaging
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Solution Overview
Problem
Existing semiconductor manufacturing processes face challenges in efficiently integrating through silicon vias (TSVs) into semiconductor devices for advanced packaging, particularly in achieving reliable electrical connections and cost-effective manufacturing.
Innovation Solution
A method involving the formation of through silicon vias (TSVs) within the semiconductor substrate, followed by fusion bonding with a reclaim silicon substrate, and subsequent planarization processes to create integrated circuit components with enhanced electrical connectivity and reduced manufacturing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through silicon vias (TSVs) are integrated into semiconductor devices for advanced packaging, then electrical connectivity is improved, but manufacturing complexity increases
Solution Approach 1:
The manufacturing process is divided into distinct stages: forming TSVs in the first substrate, bonding the second substrate, and then planarizing to expose the TSVs. This segmentation allows each step to be optimized independently, reducing overall manufacturing complexity while maintaining electrical connectivity reliability
Solution Approach 2:
The TSVs are formed and prepared in the first substrate before bonding occurs. This preliminary action allows the TSVs to be pre-configured with appropriate dimensions and materials, simplifying the subsequent bonding and planarization steps while ensuring reliable electrical connections
2Ease of manufacture
If fusion bonding with reclaim silicon substrate is used, then manufacturing costs are reduced, but bonding reliability may be compromised
Solution Approach 1:
The bonding process parameters (temperature, pressure, time) are optimized to achieve reliable bonding between the first substrate and the reclaim silicon substrate. By carefully controlling these parameters, the patent ensures bonding reliability while utilizing cost-effective reclaim silicon material
Solution Approach 2:
A bonding interface is created between the first substrate and the reclaim silicon substrate that ensures electrical and mechanical reliability. The bonding process acts as an intermediary step that connects dissimilar materials (standard silicon and reclaim silicon) with consistent performance
3Reliability
If planarization processes are performed to expose TSVs, then electrical connections are improved, but processing time increases
Solution Approach 1:
The planarization step is combined with the bonding process, where the second substrate is bonded to the first substrate and the planarization occurs simultaneously or in an integrated manner. This merging reduces the number of separate processing steps and decreases overall processing time while still achieving the necessary TSV exposure for electrical connections
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method enables efficient integration of TSVs, enhancing electrical connectivity and reducing manufacturing costs by utilizing a reclaim silicon substrate and advanced bonding techniques, resulting in improved semiconductor device performance.
Implementation Method 1
fusion bonding with a reclaim silicon substrate
Data Source
AI summary
A semiconductor structure includes a first semiconductor device, a second semiconductor device, a connection device and a redistribution circuit structure. The first semiconductor device is bonded on the second semiconductor device. The connection device is bonded on the second semiconductor device and arranged aside of the first semiconductor device, wherein the connection device includes a first substrate and conductive vias penetrating through the first substrate and electrically connected to the second semiconductor device. The redistribution circuit structure is located over the second semiconductor device, wherein the first semiconductor device and the connection device are located between the redistribution circuit structure and the second semiconductor device. The redistribution circuit structure and the first semiconductor device are electrically connected to the second semiconductor device through the conductive vias of the connection device.