3D Semiconductor TSV Reduction via Serial Data Transmission

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Solution Overview

Problem

Three-dimensional semiconductor apparatuses face challenges in reducing the number of through-silicon vias (TSVs) required for data input/output connections, which increases chip size and complicates data transmission due to the large number of data lines, leading to issues with fabrication area and current consumption.

Innovation Solution

A semiconductor apparatus configuration with independent write and read data transmission units using TSVs, allowing for reduced TSV count by separating data input/output lines into serial and parallel paths and using output timing adjustment units to manage signal skew, thereby improving data transmission efficiency.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If the number of data input/output lines is increased to handle large data transmission, then the data transmission capacity is improved, but the number of TSVs required increases, reducing the chip fabrication area

Engineering Contradiction:
Improvedata transmission capacityVSAvoidchip fabrication area
Core Design Contradiction:
Quantity of substanceVSArea of stationary object

Solution Approach 1:

The patent segments the data transmission function into two separate chips: a first chip that converts parallel data to serial data, and a second chip that converts serial data back to parallel data. This segmentation allows the use of fewer TSVs for connection while maintaining high data transmission capacity through serial communication protocols.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent transitions from parallel data transmission (multiple simultaneous data lines) to serial data transmission (single time-multiplexed data line). This dimensional change in data transmission approach reduces the number of TSVs from potentially hundreds to just a few, significantly increasing chip fabrication area.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Adaptability or versatility

If the number of TSVs is increased to connect all data input/output lines, then the data transmission connectivity is improved, but the layout margin of the chip is reduced

Engineering Contradiction:
Improvedata transmission connectivityVSAvoidlayout margin
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent divides the data transmission system into separate functional blocks on different chips, with the first chip handling parallel-to-serial conversion and the second chip handling serial-to-parallel conversion. This segmentation reduces inter-chip connection requirements and improves layout flexibility.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If all data signals are transmitted through TSVs between chips, then the electrical connection is simplified, but the current consumption increases due to large load

Engineering Contradiction:
Improveelectrical connection simplicityVSAvoidcurrent consumption
Core Design Contradiction:
Device complexityVSUse of energy by moving object

Solution Approach 1:

The patent segments the data transmission architecture into two chips with dedicated conversion functions, allowing the use of fewer TSVs with lower individual current loads. The serial communication protocol further reduces the total current consumption compared to driving numerous parallel signals across TSVs.

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS8837191B2Semiconductor apparatus
Publication Date: 2014.09.16 SK HYNIX INC
  • US8837191B2 patent drawing
  • US8837191B2 patent drawing
  • US8837191B2 patent drawing

AI summary

A semiconductor apparatus includes a multi-chip module which multi-chip module comprises a first and a second chips. The semiconductor apparatus comprises a first data line in the first chip to carry first read data; a first controller, in the first chip, configured to generate first output data on a first output data line in the first chip based on the first read data transmitted from the first data line; a first data transmitter configured to electrically connect the first output data line to the second chip.