3D Semiconductor Tunnel Insulating Structure
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Solution Overview
Problem
The integration density of semiconductor devices is limited by the 2-dimensional arrangement of memory cells, necessitating a method to increase density through 3-dimensional structuring while maintaining film quality, particularly in tunnel insulating layers.
Innovation Solution
A 3-dimensional semiconductor device is developed with a multilayered tunnel insulating structure, where the first tunnel insulating layer is a thermal oxide layer and the second is formed through radical, dry, or wet oxidation processes, preventing shallow trap layers and improving interface characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are arranged 2-dimensionally on a semiconductor substrate, then the device structure is simple and manufacturing is easier, but the integration density is limited and cannot be further increased
Solution Approach 1:
The patent transitions from 2-dimensional memory cell arrangement to 3-dimensional arrangement by forming vertical channel layers that extend through stacked insulating and conductive patterns. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, allowing memory cells to be arranged in three dimensions rather than confined to a single plane.
2Reliability
If a single-layer tunnel insulating structure is used, then the manufacturing process is simpler, but shallow trap layers form and film quality deteriorates
Solution Approach 1:
The tunnel insulating layer is divided into multiple sub-layers with different materials and functions. The first tunnel insulating layer provides electrical insulation, the second tunnel insulating layer prevents shallow trap formation, and the thermal oxide layer ensures high-quality interface characteristics. This segmentation of the single tunnel insulating layer into multiple functional layers improves overall film quality and device reliability.
Solution Approach 2:
The patent employs a composite tunnel insulating structure combining different materials including silicon oxide, silicon nitride, and thermal oxide layers. Each material contributes specific properties: silicon oxide for insulation, silicon nitride for trap prevention, and thermal oxide for interface quality. This composite structure leverages the advantages of multiple materials to achieve superior film quality that cannot be obtained with a single material.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The multilayered tunnel insulating structure enhances film quality and device performance by preventing shallow trap layers, thereby improving cycling and retention characteristics of the semiconductor device.
Implementation Method 1
a first tunnel insulating layer in contact with the charge storage layer is formed of a thermal oxide layer
Implementation Method 2
a second tunnel insulating layer formed to surround the first tunnel insulating layer
Data Source
AI summary
A semiconductor device and a method of manufacturing the same are provided. The device includes insulating patterns and conductive patterns stacked alternately, a channel layer formed through the insulating patterns and the conductive patterns, a tunnel insulating layer formed to surround sidewalls of the channel layer, and a charge storage layer formed to surround the tunnel insulating layer. An interfacial surface of the tunnel insulating layer in contact with the charge storage layer includes a thermal oxide layer.