Semiconductor Twin Cell Data Erasure Security via Scramble Segmentation
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Solution Overview
Problem
In semiconductor devices with twin cells holding complementary data, the difference in threshold voltages between cells can persist after erasure, leading to security issues when attempting to read the previous write state, and existing solutions fail to adequately address this problem.
Innovation Solution
A semiconductor device design that includes a scramble unit for processing data to be written into twin cells, a write unit for writing scramble data into a separate memory cell, and a descramble unit for reading data, ensuring that both the write data and scramble data are required for erasure, preventing incorrect read states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If twin cell data is erased to improve security, then data confidentiality is enhanced, but threshold voltage differences between cells persist causing incorrect read states
Solution Approach 1:
The patent divides the storage system into two separate storage units: a first storage unit for holding twin cell data and a second storage unit for holding scramble data. This segmentation ensures that erasing twin cell data does not automatically erase scramble data, allowing the system to maintain security while enabling correct reading of erased data states through the descramble unit.
Solution Approach 2:
The patent introduces a descramble unit as an intermediary component that receives data from the first storage unit and uses scramble data from the second storage unit to perform descrambling. This intermediary mechanism resolves the contradiction by enabling correct reading of erased twin cell data while maintaining security through the separate scramble data storage.
2Device complexity
If scramble data is stored in the same memory unit as twin cell data, then device complexity is reduced, but security is compromised due to persistent threshold voltage differences
Solution Approach 1:
The patent segments the storage functionality into two distinct units: the first storage unit for twin cell data and the second storage unit for scramble data. This segmentation maintains security by preventing threshold voltage differences from affecting scramble data while managing complexity through functional separation rather than physical integration.
Solution Approach 2:
The patent resolves the contradiction by adding a dimensional separation between data storage locations. Instead of storing both types of data in the same unit (zero-dimensional integration), the system uses separate storage units (spatial separation), which maintains security while the descramble unit provides the necessary processing dimension.
3Reliability
If twin cell data is erased to prevent reading of previous states, then security is improved, but the write state before erase can still be read due to persistent threshold voltage differences
Solution Approach 1:
The descramble unit serves as an intermediary that uses scramble data to correctly interpret the state of twin cell data after erasure. This intermediary mechanism prevents loss of write state information by enabling accurate reading of erased data through the descrambling process, while maintaining security through the separate scramble data storage unit.
Solution Approach 2:
The system implements feedback through the descramble unit that uses scramble data to correct and verify the state of twin cell data. This feedback mechanism ensures that erased data can be accurately read and verified, preventing information loss while maintaining security through the feedback-based verification process.
Data Source
AI summary
A semiconductor device includes a first storage unit including twin cells which are electrically rewritable and complementarily store 1-bit data based on a difference in a threshold voltage, a second storage unit including a memory cell which is electrically rewritable, data stored in the memory cell being erased when data in the twin cells is erased, at least one scrambler subjecting first data to a scramble processing by using scramble data to generate second data, a first write circuit which writes the second data into the twin cells in the first storage unit, a second write circuit which writes the scramble data into the memory cell in the second storage unit, and at least one descrambler subjecting the second data read from the first storage unit to a descramble processing by using the scramble data read from the second storage unit.