Semiconductor Two-Stage Register for Word Line Disturbance

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Solution Overview

Problem

Current semiconductor memory devices require large memory spaces to monitor word line access, leading to inefficiencies and increased coupling effects between word lines, which result in data loss due to word line disturbance.

Innovation Solution

A semiconductor device with a two-stage register system, where a first stage register stores events for a longer period and a second stage register stores events for a shorter period, with a controller selecting and transferring events with high reference values to the first stage register, reducing memory requirements and mitigating word line disturbance by monitoring only selected word lines.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a single large register is used to store all word line access events, then complete event monitoring is achieved, but the memory space becomes excessively large (4.5 Mb)

Engineering Contradiction:
Improveevent monitoring completenessVSAvoidmemory space
Core Design Contradiction:
Measurement precisionVSQuantity of substance

Solution Approach 1:

The patent divides the single large register into two smaller registers: a first stage register storing events for a first period, and a second stage register storing events for a second period. This segmentation reduces the memory space required for each register while maintaining comprehensive event monitoring capabilities through the combined storage of both stages.

Inventive Principle:
Principle #1Segmentation

2Measurement precision

If all word lines are monitored continuously, then complete access tracking is achieved, but coupling effects between word lines worsen causing data loss

Engineering Contradiction:
Improveaccess tracking accuracyVSAvoidword line disturbance
Core Design Contradiction:
Measurement precisionVSObject-affected harmful factors

Solution Approach 1:

The patent extracts and monitors only selected word lines that meet specific criteria (events with reference values larger than a threshold) rather than continuously monitoring all word lines. This selective monitoring approach reduces the overall monitoring activity, thereby minimizing coupling effects and disturbance between word lines while still capturing significant access patterns.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent implements periodic monitoring with two different time periods: a first period for the first stage register and a second period for the second stage register. By monitoring events periodically rather than continuously, the system reduces the frequency of word line toggling and associated disturbance effects while maintaining effective access tracking over the monitoring periods.

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If monitoring coverage is increased to track all significant word line accesses, then event detection capability improves, but the register size increases proportionally

Engineering Contradiction:
Improveevent detection capabilityVSAvoidregister size
Core Design Contradiction:
Adaptability or versatilityVSQuantity of substance

Solution Approach 1:

The patent applies local quality by assigning different monitoring characteristics to different stages: the first stage register handles events for a longer first period, while the second stage register handles events for a shorter second period. This allows the system to maintain comprehensive event detection capability across different time scales while keeping each register's size manageable through specialized local functions.

Inventive Principle:
Principle #3Local quality

Data Source

PatentUS9129672B2Semiconductor device and operating method thereof
Publication Date: 2015.09.08 SK HYNIX INC
  • US9129672B2 patent drawing
  • US9129672B2 patent drawing
  • US9129672B2 patent drawing

AI summary

A semiconductor device includes a first stage register for storing events occurring for a first period, a second stage register for storing events occurring for a second period shorter than the first period and a controller for controlling the second stage register to select events from the second stage register each having a reference value larger than a second threshold value to the first stage register and for controlling the first stage register to store events which are selected from the second stage register.