Semiconductor Substrates with Undercut Structures for PSOI Fabrication
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Solution Overview
Problem
Current methods for fabricating pseudo silicon-on-insulator (PSOI) structures are expensive and face technological challenges, particularly in achieving the desired geometries and density for semiconductor devices like DRAMs, where leakage and second-order effects become significant as components miniaturize.
Innovation Solution
A method involving the formation of n-doped regions in a semiconductor substrate, followed by selective etching to create undercut structures, which are then used to fabricate PSOI structures, allowing for improved heat dissipation and breakdown voltage without the need for additional spacers or complex etching steps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional wet etch chemistries are used to etch silicon, then isotropic etching is achieved, but the desired geometries and density for semiconductor devices cannot be obtained
Solution Approach 1:
The patent changes the chemical parameters of the etching process by using a hydroxide-based wet etchant (such as KOH or TMAH) instead of conventional isotropic etchants. This parameter change enables anisotropic etching that exploits the crystallographic structure of silicon to create the desired vertical sidewalls and undercut geometries, resolving the contradiction between achieving precise geometries and maintaining ease of manufacture
Solution Approach 2:
The patent employs a composite approach by combining a hydroxide-based wet etchant with a buffered solution (containing organic acids like acetic acid or citric acid). This composite etching system provides both the anisotropic etching capability needed for precise geometries and the buffering action that controls etching rate and prevents excessive undercutting, thereby achieving manufacturing precision without excessive fabrication complexity
2Productivity
If components are miniaturized to achieve higher circuit density, then IC performance is improved, but leakage and second order effects become significant
Solution Approach 1:
The patent introduces a vertical dimension to the device structure by creating undercut regions that extend laterally beneath the active area. This dimensional change allows for better electrical isolation and reduced leakage current in miniaturized devices, as the undercut structures can serve as isolation regions or support for dielectric materials that prevent charge leakage, thereby maintaining reliability at higher circuit densities
Solution Approach 2:
The patent uses hydroxide-based etchants as an intermediary process tool to create undercut structures that subsequently serve as isolation features. These undercut regions, formed by the selective etching action, act as intermediaries that electrically isolate adjacent active areas and reduce leakage paths, enabling high-density circuits to maintain low leakage current
3Manufacturing precision
If PSOI structures are fabricated using conventional methods, then the structures can be formed, but fabrication costs are high and additional spacers or complex etching steps are required
Solution Approach 1:
The patent extracts the spacer formation step from the conventional PSOI fabrication sequence by using the undercut structure itself to define the boundaries of the active area. The lateral etching that creates the undercut automatically provides the isolation geometry without requiring separate spacer deposition and patterning steps, thereby reducing device complexity while maintaining manufacturing precision
Solution Approach 2:
The patent performs preliminary undercut etching before forming the final active area structures. This preliminary action creates the isolation geometry in advance, which then serves as a template or guide for subsequent processing steps. By establishing the lateral boundaries early in the process, the need for complex spacer formation and multiple etching steps is eliminated, simplifying the overall fabrication process while maintaining precise geometry control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces fabrication costs and enhances semiconductor device performance by minimizing leakage current and improving breakdown voltage, while also simplifying the fabrication process and increasing die-per-wafer yield.
Implementation Method 1
The etching is initiated by the HNO3, which forms a layer of silicon dioxide on the silicon, while the HF dissolves the silicon dioxide
Implementation Method 2
The etching is initiated by the HNO3, which forms a layer of silicon dioxide on the silicon
Data Source
AI summary
An intermediate semiconductor structure that comprises a substrate and at least one undercut structure formed in the substrate is disclosed. The undercut feature may include a vertical opening having a lateral cavity therein, the vertical opening extending below the lateral cavity. The lateral cavity may include faceted sidewalls.