Semiconductor Package Underfill Layout for Smaller Chip Footprint
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Solution Overview
Problem
The challenge in semiconductor packages is to minimize the size of the underfill material layer while maintaining effective chip connections, as the underfill material often spreads and increases the package size.
Innovation Solution
A semiconductor package design with a perpendicular side surface underfill material layer and a protrusion on the upper surface, combined with a masking tape to control the underfill material flow, allowing for offset-stacked chip structures and minimizing the underfill material's footprint.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the underfill material layer is applied to cover the chip connection bump, then the chip connection reliability is improved, but the package size increases
Solution Approach 1:
The underfill material layer is segmented into a first underfill material layer and a second underfill material layer with different viscosities. The first layer (lower viscosity) provides initial coverage and filling, while the second layer (higher viscosity) maintains the desired shape and prevents excessive spreading, thus achieving reliable chip connection without excessive package size increase
Solution Approach 2:
The viscosity parameter of the underfill material is changed between layers. The first underfill material layer has a viscosity of 100-1000 cP for easy flow and filling, while the second layer has a viscosity of 1000-10000 cP to prevent excessive spreading. This parameter change allows the underfill to achieve proper coverage for reliability while controlling the final footprint to minimize package size
2Reliability
If the underfill material layer spreads to cover more area, then the chip connection reliability is improved, but the manufacturing precision deteriorates
Solution Approach 1:
The underfill application process is segmented into two stages with different material properties. The first stage uses low-viscosity material that flows to ensure complete coverage of the chip connection bump and surrounding areas. The second stage uses high-viscosity material that is applied after the first layer partially cures, providing dimensional control and preventing excessive spreading, thus achieving both reliability and manufacturing precision
Solution Approach 2:
The first underfill material layer is applied preliminarily to ensure complete coverage and filling of the chip connection bump area. After this preliminary layer is applied and partially cured, the second underfill material layer is then applied to define the final boundaries and prevent excessive spreading, achieving both reliable coverage and precise dimensional control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design optimizes the underfill material size, reducing the overall semiconductor package size without increasing the package substrate's dimensions, thereby enhancing miniaturization and weight reduction.
Implementation Method 1
providing an underfill material layer having viscosity between the controller chip and the package substrate, curing the underfill material layer after flow of the underfill material layer is stopped by the masking tape
Data Source
AI summary
A semiconductor package includes a package substrate including an upper pad on an upper surface of the package substrate, a first chip structure including a plurality of first chips offset-stacked in a first direction, a controller chip on the package substrate and apart from the first chip structure in a horizontal direction, a chip connection bump between the package substrate and the controller chip, and an underfill material layer covering the chip connection bump, wherein a side surface of the underfill material layer is perpendicular to the package substrate.