Stacked Semiconductor Chip Underfill Thermal Management
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Solution Overview
Problem
The challenge in the electronics industry is to effectively dissipate heat generated in semiconductor packages, which is exacerbated by the use of multiple semiconductor chips in a single package, leading to thermal management issues.
Innovation Solution
A method for fabricating a semiconductor device that involves bonding semiconductor chips with film-type underfill materials and using a capillary underfill method to fill spaces and cover side surfaces, while also employing plasma treatment to enhance thermal characteristics and electrical connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple semiconductor chips are stacked in a single package, then device functionality and integration are improved, but heat dissipation becomes more difficult
Solution Approach 1:
The patent transitions from planar chip arrangement to three-dimensional stacked configuration, enabling multiple chips to be integrated vertically. This dimensional change increases device functionality and integration density while managing thermal challenges through the stacked architecture and associated thermal management structures.
Solution Approach 2:
The patent introduces underfill materials as intermediary substances between chips and substrate. These underfill materials serve dual functions: providing mechanical support and stress relief for the stacked chips, and facilitating thermal conduction pathways from the chips to the substrate, thereby addressing both structural and thermal management requirements.
2Strength
If film-type underfill material is used for bonding chips, then bonding strength and electrical connectivity are improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies preliminary plasma treatment to the chip and substrate surfaces before bonding. This pre-treatment modifies surface properties to enhance adhesion of the underfill material, ensuring strong bonding without requiring complex bonding process parameters or additional bonding layers.
Solution Approach 2:
The patent utilizes plasma treatment to change the surface energy and wettability parameters of the chip and substrate surfaces. This parameter modification enables the underfill material to spread uniformly and bond effectively, achieving strong adhesion through controlled surface property changes rather than complex mechanical bonding structures.
3Temperature
If plasma treatment is applied to enhance thermal characteristics, then thermal conduction is improved, but processing time and energy consumption increase
Solution Approach 1:
The patent employs plasma treatment as a periodic surface preparation step in the fabrication process. By applying plasma treatment at specific stages (before underfill material application), the process achieves effective surface modification for enhanced thermal and adhesive properties without requiring continuous plasma exposure, thereby balancing treatment effectiveness with processing efficiency.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the thermal characteristics of semiconductor packages by efficiently managing heat dissipation and enhancing electrical connectivity between chips, thereby addressing the thermal management challenges in multi-chip stacked packages.
Implementation Method 1
plasma-treating the mounting substrate, the first semiconductor chip, and the second semiconductor chip
Implementation Method 2
forming a second underfill material, which covers the first connection terminals, fills a space between the mounting substrate and the first semiconductor chip, and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip, by using a capillary underfill method
Data Source
AI summary
A semiconductor device and a method of fabricating the same includes providing a first semiconductor chip which has first connection terminals, providing a second semiconductor chip which comprises top and bottom surfaces facing each other and has second connection terminals and a film-type first underfill material formed on the bottom surface thereof, bonding the first semiconductor chip to a mounting substrate by using the first connection terminals, bonding the first semiconductor chip and the second semiconductor chip by using the first underfill material, and forming a second underfill material which fills a space between the mounting substrate and the first semiconductor chip and covers side surfaces of the first semiconductor chip and at least part of side surfaces of the second semiconductor chip.