Semiconductor Stack Underlayer for Strained Nanosheet Defect Control

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Solution Overview

Problem

Existing semiconductor devices face challenges in maintaining strain in nanowires and nanosheets without introducing defects, as conventional underlayers can generate defects in the stack, affecting the lattice parameter and device performance.

Innovation Solution

A stack comprising sacrificial layers and channel layers with distinct lattice parameters, supported by an underlayer with a matching lattice parameter that allows the stack to relax coherently, minimizing defect introduction and maintaining strain through careful layer thickness and composition selection.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional underlayers are used to support the nanowire/nanosheet stack, then the stack can be formed and maintained, but defects are generated in the stack affecting lattice parameter and device performance

Engineering Contradiction:

Improvedevice performanceVSAvoiddefect generation

Core Design Contradiction:

ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent changes the lattice parameter of the underlayer to match the relaxed lattice parameter of the nanowire/nanosheet stack. This parameter matching eliminates lattice mismatch dislocations and prevents defect generation while maintaining structural support, thereby improving device performance without introducing harmful defects

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The underlayer acts as an intermediary between the substrate and the nanowire/nanosheet stack. By having the underlayer assume the relaxed lattice parameter, it mediates the strain in the stack, allowing the nanowires/nanosheets to maintain their strained configuration without transferring defects from the substrate

Inventive Principle:

Principle #24Intermediary (Mediator)

2Object-generated harmful factors

If the nanowire/nanosheet stack is allowed to relax coherently, then the lattice parameter matches the underlayer, but strain is reduced affecting current transport characteristics

Engineering Contradiction:

Improvedefect generationVSAvoidcurrent transport characteristics

Core Design Contradiction:

Object-generated harmful factorsVSReliability

Solution Approach 1:

The patent segments the structure into three distinct functional zones: the substrate (which can have any lattice parameter), the underlayer (which matches the relaxed lattice parameter and provides defect-free support), and the nanowire/nanosheet stack (which maintains strain for performance). This segmentation allows each layer to optimize its function without compromising the others

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The underlayer with matched lattice parameter serves as a mediator that decouples the substrate from the strained stack. It allows the stack to maintain its strained configuration for optimal current transport while the underlayer absorbs any lattice mismatch, preventing defect generation

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively inhibits plastic relaxation and defect generation in the stack, maintaining strain and improving current transport characteristics in semiconductor devices like FETs, enhancing hole and electron mobility without introducing new defects from the underlayer.

Implementation Method 1

an underlayer on which the plurality of sacrificial layers and the at least one channel layer are disposed in which a sacrificial layer is in contact with the underlayer, and in which the underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently

Methodology Applied

Scientific EffectLattice matching:

Implementation Method 2

Compressive strain in a channel of an FET may provide increased hole mobility for p-channel FETs, whereas tensile strain in a channel of an FET may provide increased electron mobility for n-channel FETs

Methodology Applied

Scientific EffectStrain:

Implementation Method 3

at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter

Methodology Applied

Scientific EffectLattice parameter mismatch:

Data Source

PatentUS10283638B2Structure and method to achieve large strain in NS without addition of stack-generated defects

Publication Date: 2019.05.07 SAMSUNG ELECTRONICS CO LTD

AI summary

A stack for a semiconductor device and a method for making the stack are disclosed. The stack comprises a plurality of sacrificial layers in which each sacrificial layer comprises a first lattice parameter; and at least one channel layer comprising a second lattice parameter that is different from the first lattice parameter and in which each channel layer is disposed between and in contact with two sacrificial layers. The stack is formed on an underlayer in which a sacrificial layer is in contact with the underlayer. The underlayer comprises a third lattice parameter that substantially matches the lattice parameter that the plurality of sacrificial layers and the at least one channel layer would have if the plurality of sacrificial layers and the at least one channel layer were was allow to relax coherently.