Semiconductor Unit Cell Area Reduction via Segmented Bit Line Contacts
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Solution Overview
Problem
The complexity of manufacturing vertical channel MOS transistors leads to increased area occupation and poor contact properties due to complicated etching processes and small margins for burying metal bit lines, necessitating a method to secure device characteristics without increasing unit cell area.
Innovation Solution
A semiconductor integrated circuit device with shared word lines and bit lines, where gate electrodes and bit line contacts are arranged to reduce the area occupied by unit memory cells, and a method involving the formation of word lines and bit lines with specific spacings and contacts to minimize the number of manufacturing processes and improve contact properties.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If vertical channel MOS transistor is used to reduce unit cell area, then area occupation is reduced, but manufacturing process complexity increases due to complicated etching processes
Solution Approach 1:
The bit line contact structure is segmented into multiple parts: a first bit line contact formed in the semiconductor substrate, and a second bit line contact formed on the first bit line contact. This segmentation allows each contact to be formed through separate, simpler manufacturing processes rather than requiring complex single-step formation, thereby reducing manufacturing complexity while maintaining the vertical channel MOS transistor's area advantages
Solution Approach 2:
The patent transitions from planar contact formation to vertical stacked contact formation. By forming bit line contacts in multiple layers (first contact in substrate, second contact on first contact), the solution moves the contact structure into the vertical dimension, enabling simplified process formation while achieving the required electrical connections for reduced unit cell area
2Area of stationary object
If metal bit line is buried in predefined space to reduce area, then unit cell area is reduced, but contact property with drain becomes poor due to small process margin
Solution Approach 1:
The bit line contact path is divided into two separate contact structures: a first bit line contact extending from the drain region, and a second bit line contact formed on top of the first contact. This segmentation creates larger process margins for each individual contact formation, improving contact reliability while maintaining the compact unit cell area through vertical stacking rather than lateral expansion
Solution Approach 2:
Instead of attempting to form a single complex buried contact in the lateral plane with small process margins, the patent uses vertical stacking to create multi-layer contacts. This dimensional transition provides adequate process margin for each contact formation step while achieving the required electrical connection, thereby improving reliability without increasing unit cell area
Data Source
AI summary
A semiconductor integrated circuit device includes a semiconductor substrate; a plurality of word lines extending parallel to one another on the semiconductor substrate; a plurality of bit lines extending parallel to one another on the semiconductor substrate and arranged to intersect the word lines, thereby delimiting a plurality of crossing regions and a plurality of unit memory cells; a plurality of gate electrodes formed to control respective pairs of unit memory cells adjacent to each other with the word lines interposed therebetween and to contact corresponding word lines on one sides of the crossing regions; storage node contacts respectively formed in spaces of the unit memory cells; and a plurality of bit line contacts formed to contact the respective bit lines on one sides of the crossing regions.