Semiconductor Unit Terminal Arrangement for Parasitic Inductance Reduction

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Solution Overview

Problem

Existing power semiconductor devices face challenges in reducing parasitic inductance, particularly in two-in-one semiconductor modules used for half-wave rectifier circuits, which leads to surge voltages during switching operations and complicates the construction of high-power semiconductor units.

Innovation Solution

The semiconductor unit design features first and second main circuit terminals arranged in specific configurations on opposing sides of a semiconductor unit, allowing for easy construction of half-wave rectifier circuits with reduced parasitic inductance by arranging the units in a way that the first main circuit terminals are on one side and the second on the other, with connectors and output terminals connected accordingly.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If busbars are arranged parallel to connect positive and negative terminals, then parasitic inductance is reduced, but device complexity increases

Engineering Contradiction:

Improveparasitic inductance reductionVSAvoidbusbar arrangement complexity

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The semiconductor unit is divided into multiple independent semiconductor devices, each with its own terminal arrangement. This segmentation allows the current paths to be distributed and arranged in a compact pattern without requiring complex interconnections between devices, thus reducing parasitic inductance while maintaining simplicity.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

Multiple semiconductor devices are combined into a single unit with a unified terminal structure. The first and second main circuit terminals are merged into a single arrangement pattern that serves all devices, eliminating the need for separate busbar connections for each device and reducing overall complexity.

Inventive Principle:

Principle #5Merging (Combining)

2Power

If multiple semiconductor devices are integrated in parallel, then current capacity increases, but parasitic inductance reduction becomes more difficult

Engineering Contradiction:

Improvecurrent capacityVSAvoidparasitic inductance control

Core Design Contradiction:

PowerVSReliability

Solution Approach 1:

The unit contains multiple independent semiconductor devices (first, second, third, and fourth devices) that are segmented and arranged in a specific pattern. Each device has its own current path, allowing parallel current flow while maintaining compact loop areas that minimize parasitic inductance.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The terminals are arranged in a two-dimensional pattern on the sealing body surface rather than linearly. The first main circuit terminals are positioned at corners and the second main circuit terminal at the center, creating a planar distribution that reduces current path length and parasitic inductance while accommodating multiple devices in parallel.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of operation

If terminals are arranged on opposite sides of the semiconductor unit, then ease of connection improves, but parasitic inductance increases

Engineering Contradiction:

Improveconnection easeVSAvoidparasitic inductance

Core Design Contradiction:

Ease of operationVSReliability

Solution Approach 1:

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11289466B2Semiconductor unit, semiconductor module, and semiconductor device

Publication Date: 2022.03.29 FUJI ELECTRIC CO LTD

AI summary

A semiconductor unit includes transistor chips; first main circuit terminals that are electrically connected to first main electrodes of the transistor chips; second main circuit terminals that are electrically connected to second main electrodes of the transistor chips; and a sealing body that has two sides and positioned on opposite sides from one another in one direction and that seals the transistor chip and the first and second main circuit terminals except for a portion of each of the first and second main circuit terminals. Moreover, the first main circuit terminals are respectively arranged in both corners of the one side and in a center of the other side of the two sides of the sealing body, and the second main circuit terminals are respectively arranged in a center of the one side and in both corners of the other side of the sealing body.