Semiconductor Device Up-Drain Structure Reducing On-Resistance
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Solution Overview
Problem
Conventional semiconductor devices with electrodes on one main surface face issues of high on-resistance due to concentrated current paths and increased chip size, as well as leak currents caused by depletion layer expansion, which necessitate larger chip areas and higher on-resistance.
Innovation Solution
A semiconductor device with a semiconductor substrate, a device region, and an impurity region surrounding the device region, where the impurity region acts as a conductive path and is connected to a second electrode, dispersing current paths across the chip circumference and reducing on-resistance, while also preventing depletion layer expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If electrodes are disposed on one main surface of the chip, then the device structure is simplified and ease of manufacture is improved, but current paths concentrate heavily leading to high on-resistance
Solution Approach 1:
The single electrode on one main surface is segmented into multiple electrode regions distributed around the peripheral portion of the chip. This segmentation disperses the current paths into multiple separate routes through the semiconductor layer, preventing current concentration and reducing on-resistance while maintaining the simplified single-surface electrode structure.
Solution Approach 2:
The electrode configuration transitions from a centralized single-point contact to a distributed peripheral arrangement, utilizing the circumferential dimension of the chip. This dimensional redistribution of electrode positions creates multiple current path routes through the semiconductor layer, effectively reducing on-resistance without complicating the manufacturing process.
2Device complexity
If electrodes are disposed on one main surface of the chip, then device complexity is reduced, but chip area increases to accommodate current path requirements
Solution Approach 1:
The electrode arrangement utilizes the peripheral circumferential dimension of the chip rather than requiring additional area in the planar dimension. By positioning multiple electrode regions around the chip's perimeter, the design efficiently uses the available chip circumference to create multiple current paths without increasing the overall chip footprint.
Solution Approach 2:
The semiconductor layer is designed with differentiated local properties: a first semiconductor region with higher resistivity and a second semiconductor region with lower resistivity. This local quality variation optimizes current distribution in different areas, allowing efficient current flow through the semiconductor layer while maintaining a compact chip area and simple device structure.
3Reliability
If impurity region is added to surround the device region, then depletion layer expansion is prevented, but device region area is reduced
Solution Approach 1:
The semiconductor layer is divided into regions with different impurity concentrations: a first semiconductor region with higher resistivity (lower impurity concentration) and a second semiconductor region with lower resistivity (higher impurity concentration). This local quality differentiation allows the high-resistivity region to effectively control depletion layer expansion while the low-resistivity region maintains adequate current conduction, optimizing both reliability and effective device area utilization.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces on-resistance by dispersing current paths and prevents depletion layer expansion, allowing for a smaller chip size without increasing on-resistance, and utilizes inactive regions for additional device area, effectively managing chip size and device performance.
Implementation Method 1
the impurity region acts as a conductive path and is connected to a second electrode, dispersing current paths across the chip circumference and reducing on-resistance
Implementation Method 2
an impurity region of the first general conductivity type formed on an edge portion of the semiconductor layer so as to surround the device region and to penetrate the semiconductor layer to reach the semiconductor substrate
Data Source
AI summary
Provided is a semiconductor device in which a high concentration n type impurity region to be a conductive path and a drain electrode are disposed in an outer circumferential end of the chip to be an inactive region as a device region. Thereby, an up-drain structure is obtained without reducing the device region or without increasing the size of a semiconductor chip. The provided n type impurity region and drain electrode causes a depletion layer of a substrate to be terminated without needing an additional conventional annular region or shield metal. This is because the n type impurity region and the drain electrode also function as the annular region and the shield metal, respectively. With this configuration, a MOSFET with the up-drain structure having necessary components is obtained, while avoiding a reduction of the device region or an increase of the chip area.