Low Profile Semiconductor Package Vacuum Die Securing

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Solution Overview

Problem

The increasing demand for smaller, more functional electronic systems with lower voltage and higher power consumption is hindered by the large size of multiple power switching transistors on motherboards, which occupy valuable space and have poor yields due to inadequate die securing during wirebonding.

Innovation Solution

A semiconductor device with a low profile package design, where semiconductor dice are mounted on a leadframe matrix with a mounting tape and secured using a vacuum system during wirebonding, eliminating the need for a die attach pad and reducing thermal and electrical resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If wirebonding is performed without mounting dice on die attach flags, then the package structure is simplified, but the yield deteriorates due to poor die positioning security

Engineering Contradiction:
Improvepackage structureVSAvoidyield
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The mounting tape with vacuum holes is prepared in advance during leadframe fabrication, creating a positioning system that secures dice before wirebonding begins. This preliminary positioning structure ensures die stability during the wirebonding process without requiring complex die attach flags.

Inventive Principle:
Principle #10Preliminary action

2Power

If multiple power switching transistors are used to meet high current levels, then the power consumption requirement is satisfied, but the area occupied on the motherboard increases

Engineering Contradiction:
Improvecurrent handling capabilityVSAvoidmotherboard area
Core Design Contradiction:
PowerVSArea of stationary object

Solution Approach 1:

Multiple power switching transistors are combined into a single integrated power module package. This consolidation integrates multiple transistor dice within one compact package, enabling high current handling while occupying minimal motherboard space.

Inventive Principle:
Principle #5Merging (Combining)

3Volume of moving object

If a low profile package design is implemented, then the physical size is reduced, but the thermal management becomes more challenging

Engineering Contradiction:
Improvepackage sizeVSAvoidthermal management
Core Design Contradiction:
Volume of moving objectVSTemperature

Solution Approach 1:

The mounting tape is removed after wirebonding, exposing the bottom surface of the semiconductor die. This extraction of the temporary mounting structure creates a direct thermal path from the die to the external environment, improving heat dissipation in the compact low-profile package.

Inventive Principle:
Principle #2Taking out (Extraction)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design achieves a smaller footprint, higher reliability, and lower costs by reducing on-resistance and thermal resistance, allowing for more efficient power management and reduced internal stresses due to fewer dissimilar materials and metallurgical junctions.

Implementation Method 1

The semiconductor die is secured during package assembly by positioning over a hole in the mounting tape and applying a vacuum through the hole

Methodology Applied
Scientific EffectVacuum: Vacuum

Data Source

PatentUS8574961B2Method of marking a low profile packaged semiconductor device
Publication Date: 2013.11.05 SEMICON COMPONENTS IND LLC
  • US8574961B2 patent drawing
  • US8574961B2 patent drawing
  • US8574961B2 patent drawing

AI summary

A semiconductor device (10) is made by mounting the bottom surfaces (31, 44, 54) of a semiconductor die (14) and a lead (15, 17) on a tape (12) and over a hole (19) in the tape. A vacuum is drawn through the hole to secure the die in place when the lead's top surface (43) is wirebonded to a top surface (32) of the semiconductor die. A molding material (49) is formed to encapsulate the top surface of the semiconductor die and to expose its bottom surface.