Semiconductor Variable Capacitor With P-Well Carrier Extraction
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Conventional semiconductor variable capacitors using accumulation mode MOS capacitors face issues with high parasitic resistance and uncertain capacitance due to the lack of a terminal for removing holes, which affects high-frequency characteristics and oscillation frequency stability.
Innovation Solution
A semiconductor variable capacitor structure is introduced with a p-well formed in the active region below the gate electrode, allowing holes induced in the p-type inversion layer to be extracted via a p-type contact region, stabilizing capacitance and reducing parasitic resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If accumulation mode MOS capacitor structure is used, then high-frequency characteristics are improved, but parasitic resistance increases and capacitance stability deteriorates
Solution Approach 1:
The invention divides the semiconductor substrate into distinct regions: an active region containing the accumulation mode MOS capacitor and a separate carrier removal region. This segmentation allows the capacitor to maintain its accumulation mode structure for high-frequency performance while the separate region handles carrier extraction, resolving the contradiction between speed and reliability.
Solution Approach 2:
The invention extracts the carrier removal function from the capacitor structure itself by providing a separate carrier removal terminal in a different region. This allows the capacitor to operate in accumulation mode without the parasitic resistance and instability caused by hole accumulation, while still enabling carrier extraction when needed through the separate terminal.
2Quantity of substance
If inversion mode MOS capacitor structure is used, then capacitance value is achieved, but channel resistance increases and high-frequency characteristics deteriorate
Solution Approach 1:
Instead of using the conventional inversion mode MOS capacitor structure, the invention inverts the approach by using accumulation mode MOS capacitor structure. This inversion of the conventional design allows achieving capacitance values while maintaining low channel resistance and excellent high-frequency characteristics.
3Device complexity
If no carrier removal terminal is provided, then device structure is simplified, but capacitance uncertainty increases due to hole accumulation
Solution Approach 1:
The invention introduces a carrier removal terminal in a separate region as an intermediary element. This terminal acts as a mediator that can extract accumulated carriers from the semiconductor substrate without complicating the core capacitor structure, thereby reducing capacitance uncertainty while maintaining relatively simple device architecture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration lowers channel resistance, operational voltage, and improves high-frequency characteristics by stabilizing capacitance, facilitating more precise circuit design and operation.
Implementation Method 1
a p-well formed in the active region below the gate electrode, allowing holes induced in the p-type inversion layer to be extracted via a p-type contact region
Data Source
AI summary
The semiconductor variable capacitor includes a capacitor including an n-well 16 formed in a first region of a semiconductor substrate 10, an insulating film 18 formed over the semiconductor substrate 10 and a gate electrode 20n formed above the n-well 16 with the insulating film 18 interposed therebetween; and a p-well 14 of a second conduction type formed in a second region adjacent to the first region of the semiconductor substrate 10. The gate electrode 20n has an end which is extended to the second region and formed above the p-well 14 with the insulating film 18 interposed therebetween.