Semiconductor Variable Capacitor Vt Implant Series Resistance
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Solution Overview
Problem
Semiconductor variable capacitors face challenges with high series resistance and low quality factor due to retrograde well doping concentration profiles, which impact their performance and compatibility with CMOS fabrication processes.
Innovation Solution
Incorporating a threshold voltage (Vt) implant region in the semiconductor variable capacitor structure to improve the quality factor and reduce series resistance, while using CMOS-compatible processes and separate n-well and p-well regions to enhance tuning range and linearity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If retrograde well doping concentration profile is used in semiconductor variable capacitor, then manufacturing compatibility with CMOS processes is improved, but series resistance increases and quality factor decreases
Solution Approach 1:
The patent applies local quality by implementing a threshold voltage implant region with specific doping characteristics in a localized area of the semiconductor variable capacitor. This Vt implant region is positioned between the first non-insulative region and the first semiconductor region, creating a localized doping profile that differs from the retrograde well structure. This local modification reduces series resistance in the critical path while preserving the overall retrograde well architecture for CMOS compatibility.
2Ease of manufacture
If retrograde well doping concentration profile is used in semiconductor variable capacitor, then manufacturing compatibility with CMOS processes is improved, but series resistance increases
Solution Approach 1:
The patent employs parameter changes by modifying the doping concentration profile through a threshold voltage implant process. The Vt implant region introduces a specific doping concentration and depth profile that differs from the standard retrograde well structure. This parameter modification optimizes the electrical characteristics by reducing series resistance while maintaining compatibility with existing CMOS fabrication parameters and processes.
3Reliability
If Vt implant region is added to reduce series resistance, then quality factor is improved, but device complexity increases
Solution Approach 1:
The patent applies merging by integrating the threshold voltage implant region formation into the existing semiconductor variable capacitor fabrication process. The Vt implant region is combined with the retrograde well structure and other capacitor components in a unified device architecture. This merging approach allows the series resistance reduction feature to be incorporated without requiring entirely separate processing steps or additional discrete components, thereby limiting the increase in device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The Vt implant region reduces series resistance and increases the quality factor of the semiconductor variable capacitor, improving its performance and compatibility with CMOS fabrication processes, thereby enhancing the capacitor's tuning range and voltage rating.
Implementation Method 1
forming a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region
Implementation Method 2
the thickness of a depletion region formed in a p-n junction diode is varied by changing a bias voltage to alter the junction capacitance
Implementation Method 3
a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region
Data Source
AI summary
Certain aspects of the present disclosure generally relate to a semiconductor variable capacitor, and techniques for fabricating the same, implemented using a threshold voltage implant region. For example, the semiconductor variable capacitor generally includes a first non-insulative region disposed above a first semiconductor region, a second non-insulative region disposed above the first semiconductor region, and a threshold voltage (Vt) implant region interposed between the first non-insulative region and the first semiconductor region and disposed adjacent to the second non-insulative region. In certain aspects, the semiconductor variable capacitor also includes a control region disposed above the first semiconductor region such that a capacitance between the first non-insulative region and the second non-insulative region is configured to be adjusted by varying a control voltage applied to the control region.