Semiconductor Die Stacking With Variable Pillars to Limit Warpage
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Solution Overview
Problem
Miniaturization of semiconductor devices leads to increased complexity in manufacturing, resulting in issues like poor electrical interconnection, warpage, and material wastage due to thickness differences and varying thermal expansion coefficients of components, which complicates the assembly and integration of semiconductor components.
Innovation Solution
A semiconductor structure is designed with a redistribution layer (RDL) and conductive pillars of varying heights to compensate for thickness differences between dies, ensuring uniform exposure and minimizing warpage by eliminating molding over the backsides of dies, thus improving electrical connections and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If wafer level packaging is used to assemble multiple semiconductor components, then manufacturing cost is reduced and manufacturing operations are simplified, but electrical interconnection quality deteriorates and yield loss increases due to poor connections
Solution Approach 1:
The patent segments the semiconductor components into a substrate and multiple dies, with each die being separately mounted and interconnected through conductive structures. This segmentation allows for improved electrical connections while maintaining the cost benefits of wafer-level packaging by enabling precise alignment and connection control for each component.
2Volume of moving object
If miniaturization is implemented to reduce semiconductor device size, then device footprint is reduced, but manufacturing complexity increases and leads to warpage and delamination
Solution Approach 1:
The patent applies local quality by providing different thicknesses of molding material in different regions of the semiconductor device. Specifically, the molding material has a first thickness in a first region and a second thickness in a second region, allowing compensation for warpage and delamination in specific areas without affecting the overall miniaturized design. This localized approach addresses manufacturing complexity while maintaining small device size.
3Adaptability or versatility
If multiple different integrated components are assembled on the semiconductor device, then functionality is enhanced, but manufacturing complexity increases and structure modification becomes more challenging
Solution Approach 1:
The patent implements universality by creating a standardized substrate structure with multiple mounting regions that can accommodate different types of semiconductor dies. The substrate includes a standardized interface with the packaging substrate and multiple regions for mounting different dies, allowing various functionalities to be integrated using the same base structure, thereby reducing manufacturing complexity despite enhanced functionality.
Data Source
AI summary
A method of manufacturing a semiconductor structure includes the following operations. A substrate is provided. A first conductive pillar, a second conductive pillar arid a third conductive pillar are disposed over the substrate. The first conductive pillar comprises a first height, the second conductive pillar comprises a second height, and the third conductive pillar comprises a third height. A first die is disposed over the first conductive pillar. A second die is disposed over the second conductive pillar. A first surface of the first die and a second surface of the second die are at substantially same level.