Semiconductor Line Patterns with Variable Widths via Quadruple Patterning
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Solution Overview
Problem
The challenge in semiconductor manufacturing is forming micro patterns with varying widths that exceed the resolution limitations of photolithography processes, while minimizing defects caused by process variables, and reducing the number of photolithography applications.
Innovation Solution
A semiconductor device and manufacturing method involving the formation of line patterns and active regions with variable widths using a quadruple patterning technology (QPT) process, where line patterns and spaces are repeatedly formed at a predetermined cycle, and line repetition units and space repetition units are alternately arranged to achieve the desired micro pattern widths, allowing for reduced defect rates and efficient process optimization.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography process is used to form micro patterns, then manufacturing process is simple, but resolution limitation prevents forming patterns smaller than process capability
Solution Approach 1:
The patterning process is divided into multiple sequential steps (first patterning, second patterning, third patterning) where each step forms a portion of the final pattern. This segmentation allows achieving sub-resolution dimensions by combining multiple coarser patterning steps, thereby overcoming the resolution limitation of single photolithography processes while maintaining manufacturing feasibility
Solution Approach 2:
The patent introduces a temporal dimension by repeating the patterning process multiple times at different stages. Instead of attempting to form all patterns in a single photolithography step, the process uses sequential patterning operations spaced at different times, allowing each step to work within its resolution capabilities while the cumulative effect achieves the desired fine pitch dimensions
2Manufacturing precision
If photolithography process is applied multiple times to form various width patterns, then manufacturing precision improves, but number of process steps increases
Solution Approach 1:
Multiple patterning operations are merged into a unified process flow where first, second, and third patterning steps are combined to form the complete set of line patterns with varying widths. This merging allows achieving precise width control through the cumulative effect of multiple steps while managing the overall process as an integrated sequence rather than separate operations, thereby improving manufacturing precision without completely sacrificing productivity
3Productivity
If pitch is reduced to increase device integration, then device density improves, but photolithography resolution limitation is exceeded
Solution Approach 1:
The patent performs preliminary patterning actions in sequential steps before achieving the final fine-pitch pattern. By preparing intermediate patterns through first and second patterning operations, and then using these as basis for third patterning, the process enables formation of sub-resolution pitches that would be impossible to achieve directly in a single photolithography step, thereby increasing device integration density while maintaining manufacturing precision
Data Source
AI summary
A semiconductor device includes a plurality of line patterns including at least two continuous line repetition units having, as one of the line repetition unit, four line patterns continuously arranged in a first direction and having variable widths based on location. To form the plurality of line patterns including the at least two continuous line repetition units, a plurality of reference patterns are formed repeatedly at a uniform reference pitch on a feature layer. A plurality of first spacers covering both side walls of each of the plurality of reference patterns are formed. A plurality of second spacers covering both side walls of each of the plurality of first spacers are formed by removing the plurality of reference patterns. The feature layer is etched using the plurality of second spacers as an etch mask by removing the plurality of first spacers.