Semiconductor Structure with Varying Gate Pitch for Source Drain Epitaxy
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Solution Overview
Problem
The semiconductor industry faces challenges in simultaneously forming raised epitaxial source and drain features for both memory and logic devices, as memory devices require higher transistor density and different S/D feature characteristics than logic devices, making it difficult to achieve optimal carrier mobility and prevent S/D feature merging.
Innovation Solution
A method is developed to form semiconductor devices with varying gate pitches and dielectric layer thicknesses to create distinct recess profiles for epitaxial growth, allowing for the simultaneous fabrication of raised S/D features that meet the requirements of both logic and memory devices by tuning etching processes and epitaxial growth parameters.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a single epitaxial growth process is used for both memory and logic devices, then production efficiency is improved, but the different transistor density requirements and S/D feature characteristics cannot be simultaneously satisfied
Solution Approach 1:
The patent applies local quality by creating different recess profiles in different device regions. Logic device regions receive recesses with first dimensions while memory device regions receive recesses with second dimensions, allowing each region to have optimized S/D features tailored to its specific transistor density requirements and performance characteristics.
Solution Approach 2:
The patent utilizes parameter changes by varying etching process parameters (such as etch depth, etch rate, or etch selectivity) to create different recess dimensions in different device regions. This enables the same epitaxial growth process to produce appropriately sized S/D features for both logic and memory devices by controlling the underlying recess geometry.
2Reliability
If raised S/D features are grown to improve carrier mobility in logic devices, then device performance is enhanced, but S/D features may merge in high-density memory device regions
Solution Approach 1:
The patent implements local quality by providing different recess dimensions for logic versus memory devices. Logic devices receive larger recesses that accommodate bigger raised S/D features for improved carrier mobility, while memory devices receive smaller recesses that limit S/D feature growth to prevent merging, thus locally optimizing each device type's performance.
Solution Approach 2:
The patent applies preliminary anti-action by pre-defining different recess profiles before epitaxial growth. The smaller recesses in memory device regions act in advance to constrain S/D feature growth, preventing the harmful merging effect before it can occur during the epitaxial process.
3Manufacturing precision
If different etching processes are used for logic and memory devices to create optimal recess profiles, then S/D feature characteristics are improved, but process complexity increases
Solution Approach 1:
The patent employs universality by using a single etching process that can produce different recess profiles through parameter adjustment. This multi-functional approach allows one etching process to serve both logic and memory device fabrication needs, eliminating the requirement for separate etching processes while still achieving region-specific recess characteristics.
Solution Approach 2:
The patent utilizes parameter changes to enable a single etching process to create different recess profiles. By modifying etching parameters (such as etch depth, power, pressure, or chemistry) depending on the device region being processed, the same etching equipment and process flow can generate the distinct recess dimensions required for both logic and memory devices.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of semiconductor devices with improved carrier mobility in logic devices and prevents S/D feature merging in memory devices, enhancing production efficiency by using a single etching process for both device types.
Implementation Method 1
performing a first etching process to the first dielectric layer. The first etching process removes a first portion of the first dielectric layer over the substrate
Implementation Method 2
epitaxially growing fifth and sixth pluralities of semiconductor features in the third and fourth pluralities, respectively
Data Source
AI summary
A semiconductor structure includes a substrate, first fins extending from the substrate with a first fin pitch, and second fins extending from the substrate with a second fin pitch smaller than the first fin pitch. The semiconductor structure also includes first gate structures engaging the first fins with a first gate pitch and second gate structures engaging the second fins with a second gate pitch smaller than the first gate pitch. The semiconductor structure also includes first epitaxial semiconductor features partially embedded in the first fins and adjacent the first gate structures and second epitaxial semiconductor features partially embedded in the second fins and adjacent the second gate structures. A bottom surface of the first epitaxial semiconductor features is lower than a bottom surface of the second epitaxial semiconductor features.