Semiconductor Integrated Circuit With Varying Isolation Depths
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Solution Overview
Problem
Conventional semiconductor integrated circuits face challenges in scaling down below 65 nm and integrating semiconductor structures and isolation structures of different sizes on the same substrate without increasing process cost, particularly with FinFET technology.
Innovation Solution
The integration of a multi-gate transistor device with n-well resistor and/or LDMOS device on a substrate with varying isolation structures, where the depth of first isolation structures is smaller than the second, providing electrical isolation and flexibility in device integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If FinFET technology is used to scale down below 65 nm, then device performance and channel control are improved, but integration of different-sized semiconductor structures becomes difficult
Solution Approach 1:
The substrate is divided into multiple regions with different isolation structure depths. First isolation structures with a first depth are formed in first regions, while second isolation structures with a second depth (greater than the first depth) are formed in second regions. This segmentation allows different-sized semiconductor structures to be integrated in different regions without interfering with each other, while maintaining the benefits of FinFET technology in each region.
2Adaptability or versatility
If multiple isolation structures of different sizes are formed on the same substrate, then device integration flexibility is improved, but process complexity increases
Solution Approach 1:
Instead of varying isolation structure sizes in the planar dimension, the invention introduces depth as an additional dimension. Isolation structures are formed with different depths (first depth vs. second depth) while maintaining compatibility with standard photolithography processes. This vertical differentiation allows complex device integration without proportionally increasing process complexity.
3Reliability
If deeper isolation structures are used for electrical isolation, then electrical isolation performance is improved, but manufacturing complexity and cost increase
Solution Approach 1:
Different isolation structure depths are applied locally to different regions based on specific electrical isolation requirements. Second isolation structures with greater depth are formed only in second regions where enhanced isolation is needed, while first isolation structures with standard depth suffice for first regions. This localized approach achieves necessary electrical isolation performance without uniformly increasing manufacturing complexity across the entire substrate.
Data Source
AI summary
A semiconductor integrated circuit includes a substrate, a multi-gate transistor device positioned on the substrate, and an LDMOS device positioned on the substrate. The substrate includes a plurality of first isolation structures and a plurality of second isolation structures. A depth of the first isolation structures is smaller than a depth of the second isolation structures. The multi-gate transistor device includes a plurality of first fin structures and a first gate electrode. The first fin structures are parallel with each other and spaced apart from each other by the first isolation structures. The first gate electrode is intersectionally arranged with the first fin structures, and covers a portion of each first fin structure. The LDMOS device includes a second gate electrode covering on the substrate. The LDMOS device is electrically isolated from the multi-gate transistor device by another second isolation structure.