Semiconductor Verification Apparatus High-Speed Signal Observation
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Solution Overview
Problem
Current semiconductor verification methods using hardware emulators face challenges in observing all signals due to cost constraints and hardware restrictions, making it difficult to acquire logical values of arbitrary signals inside FPGA devices efficiently.
Innovation Solution
A semiconductor verification apparatus and method that utilizes memory element calculation, loading control, and logical value calculation means to extract logical values of all signals inside semiconductor devices by controlling the loading of memory elements through JTAG (IEEE1149.1) and circuit information, allowing for high-speed signal acquisition.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If hardware emulators are used to verify semiconductor devices, then verification speed is improved, but observability of all signals deteriorates due to hardware restrictions and cost constraints
Solution Approach 1:
The patent introduces an intermediary software layer that acts as a mediator between the hardware emulator and the verification tools. This software intermediary captures signals from the hardware emulator's limited observation points and reconstructs the logical values of all signals through computational logic, thereby enabling comprehensive observability without requiring physical access to all hardware signals.
Solution Approach 2:
The patent creates a virtual copy of the hardware device's internal state and signal behavior through software modeling. By capturing the behavior of memory elements and logic circuits and replicating it in software, the system can observe and analyze all signals as if they were physically accessible, while maintaining the speed advantage of hardware emulation.
2Difficulty of detecting and measuring
If all memory elements are loaded to observe all signals, then observability is improved, but time required for signal acquisition increases
Solution Approach 1:
The patent extracts only the necessary information from memory elements to compute the logical values of target signals. Instead of loading all memory element values, the system identifies and extracts only those memory element values that are required to determine the logical state of observed signals, significantly reducing acquisition time while maintaining complete observability.
Solution Approach 2:
The patent applies partial action by loading and processing only the subset of memory elements necessary for observing specific signals, rather than loading all memory elements. This selective approach reduces the time required for signal acquisition while still achieving full observability of the target signals through computational logic.
3Difficulty of detecting and measuring
If complex loading methods are used to access memory elements, then observability is improved, but operation speed decreases
Solution Approach 1:
The patent replaces complex hardware-based loading mechanisms with software-based computational logic. Instead of using complicated hardware circuits to access all memory elements, the system uses software algorithms to compute logical values from a simplified set of captured signals, dramatically simplifying the loading process and improving operation speed.
Data Source
AI summary
A semiconductor device which can only load a logical value of an arbitrary memory element is rendered possible to allow a logical value of an arbitrary signal to be loaded at a high speed. A circuit diagram of the semiconductor device is input and a memory element required for calculating a desired signal is detected. The logical value of the memory element is loaded from the semiconductor device, and the logical value of the desired signal is determined in accordance with the logical value of the memory element and the circuit configuration.