Semiconductor Verification Signal Restriction False Error Reduction
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Solution Overview
Problem
Current semiconductor integrated circuit verification devices face inefficiencies due to high rates of false error information, requiring extensive trial and error to identify the cause of failures, especially when verifying all combinations of input signals, which is time-consuming and inefficient.
Innovation Solution
A verification device and method that includes an assertion-based verification unit, logic generating unit, signal restriction generating unit, and estimating unit to extract and evaluate signal restrictions, thereby reducing false errors and optimizing the verification process by generating signal restrictions to suppress abnormal states and false errors, and modifying assertion descriptions to prevent failures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If formal verification is used to cover all combinations of input signals, then verification completeness is improved, but the amount of false error information increases dramatically
Solution Approach 1:
The patent segments the verification process into multiple stages: initial formal verification to generate all failure information, followed by classification into true errors and false errors, and finally targeted re-verification only on true errors. This segmentation reduces the impact of false errors by isolating them from the main verification flow.
Solution Approach 2:
The patent introduces an intermediary classification mechanism that acts as a mediator between formal verification and final verification results. This classifier analyzes failure information to distinguish true errors from false errors, preventing false errors from propagating to the final verification outcome.
2Measurement precision
If trial and error method is used to identify failure causes, then verification accuracy is improved, but verification time increases tremendously
Solution Approach 1:
The patent performs preliminary classification of failure information into true errors and false errors before the final verification conclusion. This preliminary action eliminates the need for time-consuming trial and error later, as the classification results directly guide the verification inspector to true errors only.
Solution Approach 2:
The patent implements a feedback mechanism where classification results of failure information are fed back to guide subsequent verification activities. The verification inspector uses this feedback to focus on true errors identified by the classifier, avoiding wasted effort on false errors.
3Reliability
If assertion description is modified to prevent failures, then verification quality is improved, but device complexity increases
Solution Approach 1:
The patent modifies assertion descriptions by changing parameters such as adding signal restrictions and adjusting preliminary conditions based on classification results. These parameter changes prevent false errors without fundamentally altering the assertion description structure, thus limiting complexity increase.
Data Source
AI summary
According to one embodiment, a verification device of semiconductor integrated circuit includes an assertion based verification unit, a logic generating unit, a signal restriction generating unit, and an estimation unit. The assertion based verification unit performs assertion based verification of the circuit description based on the assertion description, and generates pass information when the operation of the signal described in the assertion description conforming to a preliminary condition is observed in the circuit description, or generates failure information when the operation of the signal is not observed in the circuit description. The logic generating unit extracts a signal corresponding to the failure information from the assertion description, and generates an input/output logic of the circuit description from the extracted signal. The signal restriction generating unit generates a signal restriction based on the input/output logic. The estimating unit evaluates the validity of the signal restriction.