Semiconductor Contact Formation Using Vertical Alignment Spacers
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Solution Overview
Problem
Current semiconductor technologies face challenges in forming reliable conductive contacts between gate structures and active areas, often resulting in damaged surfaces and increased contact resistance due to non-uniform lattice structures and processing damages.
Innovation Solution
The method involves forming alignment spacers with substantially vertical outer surfaces on gate structures, allowing for a conductive contact to be made with a planar, undamaged active area surface, which enhances contact area and reduces resistance by using techniques such as deposition and etching of alignment materials like Si3N4, followed by the formation of gate electrodes and ILD caps.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation methods are used to connect metal layers, then electrical connections are established, but the contact surface becomes damaged and contact resistance increases
Solution Approach 1:
The patent applies preliminary action by forming alignment spacers on gate structures before contact formation. These spacers serve as protective structures that define the contact area and prevent damage to the active region surface during subsequent processing steps. The spacers are formed with substantially vertical outer surfaces that extend beyond the gate structure, creating a protected zone for the contact formation process.
Solution Approach 2:
The alignment spacers act as intermediary structures between the gate structure and the contact region. They provide a protective barrier during contact formation, allowing the contact to be made with the planar, undamaged active area surface. The spacers mediate the interaction between processing tools and the sensitive active region, preventing direct damage while enabling reliable electrical connection.
2Reliability
If alignment spacers with substantially vertical outer surfaces are formed, then contact area is enhanced and resistance is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent applies segmentation by dividing the structure into distinct functional zones using alignment spacers. The spacers create separate regions: a protected active area for contact formation, a gate structure region, and spacer regions that define boundaries. This segmentation allows each zone to be optimized independently - the contact area is enhanced by the spacer geometry while the overall process remains manageable through clear spatial separation of functions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a more desirable contact shape and lower contact resistance by maintaining an undamaged, uniform lattice structure, thereby improving the semiconductor arrangement's performance.
Implementation Method 1
deposition and etching of alignment materials like Si3N4
Data Source
AI summary
A semiconductor arrangement and method of formation are provided. The semiconductor arrangement comprises a conductive contact in contact with a substantially planar first top surface of a first active area, the contact between and in contact with a first alignment spacer and a second alignment spacer both having substantially vertical outer surfaces. The contact formed between the first alignment spacer and the second alignment spacer has a more desired contact shape then a contact formed between alignment spacers that do not have substantially vertical outer surfaces. The substantially planar surface of the first active area is indicative of a substantially undamaged structure of the first active area as compared to an active area that is not substantially planar. The substantially undamaged first active area has a greater contact area for the contact and a lower contact resistance as compared to a damaged first active area.