Semiconductor Device Vertical Channels for Low-Leakage Compact Displays
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing semiconductor devices face challenges in achieving a minute size, short channel length, high on-state current, low cutoff current, low power consumption, and high reliability, while also requiring high-resolution displays for applications like VR, AR, and MR devices.
Innovation Solution
A semiconductor device structure comprising multiple layers with varying conductivities and metal oxides, including a first semiconductor layer with higher conductivity than a second semiconductor layer, and a conductive layer configuration that allows for a vertical-channel transistor design, reducing channel length and area occupancy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the area occupied by transistors is reduced to increase resolution, then the pixel size can be reduced and resolution can be increased, but the transistor size becomes extremely minute making manufacturing difficult
Solution Approach 1:
The patent transitions from planar transistor architecture to vertical-channel transistor architecture. The channel extends vertically through multiple layers (first semiconductor layer, second semiconductor layer, third semiconductor layer) rather than horizontally, allowing the transistor to fit within a smaller footprint area while maintaining adequate channel length for reliable operation. This dimensional change resolves the contradiction by enabling miniaturization without sacrificing manufacturing feasibility or device performance.
Solution Approach 2:
The patent employs composite semiconductor structures with multiple layers having different conductivities (first semiconductor layer with higher conductivity, second semiconductor layer with lower conductivity, third semiconductor layer). This composite approach allows optimization of different regions for different functions: high conductivity regions for current flow, low conductivity regions for channel control, enabling reliable transistor operation at minute dimensions.
2Area of stationary object
If the channel length is shortened to reduce transistor area, then the transistor size is reduced, but the cutoff current increases and on-state current decreases
Solution Approach 1:
By orienting the channel vertically rather than horizontally, the patent achieves short channel length in the planar dimension (reducing transistor area) while maintaining adequate effective channel length through the vertical stacking of semiconductor layers. This preserves current characteristics (low cutoff current, high on-state current) while minimizing footprint.
Solution Approach 2:
The patent applies different conductivity characteristics to different local regions: the first semiconductor layer has higher conductivity for efficient current transport, the second semiconductor layer has lower conductivity for effective channel control and threshold voltage adjustment, and the third semiconductor layer provides additional functionality. This local differentiation maintains current characteristics despite reduced overall channel length.
3Reliability
If multiple layers with different conductivities are used to improve transistor performance, then on-state current and cutoff current characteristics are enhanced, but the device complexity increases
Solution Approach 1:
The patent segments the semiconductor structure into distinct functional layers: first semiconductor layer (higher conductivity) for current conduction, second semiconductor layer (lower conductivity) for channel control, and third semiconductor layer for additional functionality. This segmentation enables independent optimization of each layer's properties to achieve superior electric characteristics while maintaining a systematic, manufacturable structure.
Solution Approach 2:
The multi-layer semiconductor structure serves multiple functions simultaneously: current conduction, channel control, threshold voltage adjustment, and leakage current suppression. Each layer contributes to different aspects of transistor performance, making the complex structure highly efficient and justifying the increased device complexity through enhanced functionality.
Data Source
AI summary
A semiconductor device that has both low power consumption and high performance is provided. The semiconductor device includes a first semiconductor layer, a second semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a first insulating layer, and a second insulating layer. The first insulating layer is provided over the first conductive layer. The second conductive layer is provided over the first insulating layer. The first insulating layer and the second conductive layer include an opening reaching the first conductive layer. The first semiconductor layer is in contact with a top surface of the first conductive layer, a side surface of the first insulating layer, and a top surface and a side surface of the second conductive layer. The second semiconductor layer is provided over the first semiconductor layer. The second insulating layer is provided over the second semiconductor layer. The third conductive layer is provided over the second insulating layer. A conductivity of the first semiconductor layer is higher than a conductivity of the second semiconductor layer.