Semiconductor Device Vertical Electrode Stack Integration
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity and integration density while maintaining reliability, particularly in the arrangement and connectivity of memory cells and peripheral circuits.
Innovation Solution
The semiconductor device incorporates a substrate with a cell array region and connection region, featuring vertically stacked electrodes, conductive support patterns, and insulating patterns to form a stepwise structure, along with vertical semiconductor patterns and data storage patterns, enabling efficient data storage and connectivity through a controller for improved performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells and peripheral circuits are arranged on the same substrate, then integration density is improved, but manufacturing precision deteriorates due to the complexity of simultaneous fabrication
Solution Approach 1:
The substrate is divided into a cell array region and a connection region, allowing different fabrication processes to be applied to each region independently. The cell array region undergoes a first fabrication process while the connection region undergoes a second fabrication process, enabling high integration density while maintaining manufacturing precision through regional specialization.
2Quantity of substance
If vertically stacked electrodes are used, then data storage capacity is improved, but device complexity increases due to the multi-layer structure
Solution Approach 1:
The patent transitions from planar electrode arrangement to vertically stacked electrodes, utilizing the third dimension (height) to increase data storage capacity. Multiple electrodes are stacked in the vertical direction, allowing more storage elements to be packed into the same footprint area, thereby improving capacity while managing complexity through vertical integration.
3Ease of operation
If conductive support patterns and insulating patterns are added, then connectivity is improved, but manufacturing precision deteriorates due to additional fabrication steps
Solution Approach 1:
Conductive support patterns are selectively formed in the connection region to provide mechanical support and electrical connectivity, while insulating patterns are placed in specific locations to electrically isolate different components. This localized application of different materials and structures improves connectivity where needed without unnecessarily complicating the overall fabrication process.
Data Source
AI summary
A semiconductor device and an electronic system, the device including a substrate including a cell array region and a connection region; a stack including electrodes vertically stacked on the substrate; a source conductive pattern on the cell array region and between the substrate and the stack; a dummy insulating pattern on the connection region and between the substrate and the stack; a conductive support pattern between the stack and the source conductive pattern and between the stack and the dummy insulating pattern; a plurality of first vertical structures on the cell array region and penetrating the electrode structure, the conductive support pattern, and the source structure; and a plurality of second vertical structures on the connection region and penetrating the electrode structure, the conductive support pattern, and the dummy insulating pattern.