Semiconductor Device with Vertical Fin and Exposed Corner Edge
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Solution Overview
Problem
Semiconductor devices face challenges in achieving enhanced electrical characteristics and improved integration while maintaining high reliability, speed, and multi-functionality, particularly in the design of field effect transistors.
Innovation Solution
The semiconductor device incorporates a substrate with vertically protruding active patterns and source/drain patterns formed by selective epitaxial growth, featuring semiconductor elements with varying lattice constants to provide compressive stress and improved conductivity, along with a specific geometry that includes exposed corner edges to enhance electrical performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional planar transistor structures are used, then fabrication is simpler, but electrical characteristics and integration density are limited
Solution Approach 1:
The patent transitions from conventional planar transistor structures to vertically protruding active patterns (fin structures) that extend in the vertical dimension. This dimensional change increases the effective channel area without increasing the planar footprint, thereby improving electrical characteristics (current drive capability, transconductance) and integration density while maintaining fabrication feasibility through established CMOS processes.
2Reliability
If source/drain patterns are formed without selective epitaxial growth, then manufacturing is simpler, but conductivity and electrical performance are insufficient
Solution Approach 1:
The patent employs selective epitaxial growth to form source/drain patterns with controlled crystal structure and composition parameters. By adjusting epitaxial growth conditions (temperature, pressure, gas flow, precursor ratios), the patent optimizes the semiconductor layer properties to achieve enhanced conductivity and carrier mobility, directly improving electrical performance and reliability.
Solution Approach 2:
The patent utilizes composite semiconductor structures formed through selective epitaxial growth, combining different semiconductor materials or compositions within the source/drain regions. This may include graded composition layers or heterostructure designs that optimize electrical properties by combining the advantages of different semiconductor materials.
3Productivity
If active patterns are formed without vertical protrusion, then fabrication is simpler, but integration density and electrical performance are limited
Solution Approach 1:
The patent forms active patterns with vertical protrusions (fin structures) that extend upward from the substrate surface. This vertical configuration increases the effective device area and channel length without increasing the lateral footprint, thereby achieving higher integration density. The fin structure allows multiple transistors to be packed more closely while maintaining adequate electrical performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enhances electrical characteristics and integration by optimizing the semiconductor device's structure, leading to improved reliability, speed, and functionality, particularly in memory and logic operations.
Implementation Method 1
featuring semiconductor elements with varying lattice constants to provide compressive stress and improved conductivity
Data Source
AI summary
Disclosed is a semiconductor device that comprises a substrate including a first active pattern vertically protruding from a top surface of the substrate, and a first source/drain pattern filing a first recess formed on an upper portion of the first active pattern. The first source/drain pattern comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern. The first semiconductor pattern has a first face, a second face, and a first corner edge defined when the first face and the second face meet with each other. The second semiconductor pattern covers the first face and the second face of the first semiconductor pattern and exposes the first corner edge.