3D Semiconductor Vertical Structures for Gate Integration
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Solution Overview
Problem
The increasing number of gate electrodes in semiconductor devices stacked perpendicular to the substrate surface complicates the gate forming process, leading to higher defect rates and integration challenges.
Innovation Solution
A three-dimensional semiconductor device design featuring cell and dummy vertical structures that pass through gate electrodes, with a buffer region of different material and gate contact plugs, which supports the gate electrodes and prevents defects and electrical shorts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of gate electrodes stacked perpendicular to the substrate surface is increased to achieve high integration, then the integration density is improved, but the gate forming process complexity and defect rate increase
Solution Approach 1:
The gate electrode structure is segmented into multiple stacked layers (first gate electrode, second gate electrode, third gate electrode) with distinct formation processes. Each gate electrode is formed separately through individual conformal deposition and etch steps, allowing independent optimization and control of each layer, thereby reducing overall process complexity while maintaining high integration density
Solution Approach 2:
The patent transitions from planar gate electrode arrangement to three-dimensional vertical stacking perpendicular to the substrate surface. This dimensional change enables significantly higher integration density by utilizing the vertical space above the substrate, accommodating multiple gate electrodes in the same footprint area
2Quantity of substance
If the number of gate electrodes stacked perpendicular to the substrate surface is increased to achieve high integration, then the integration density is improved, but the defect rate increases
Solution Approach 1:
A dummy gate electrode is formed in advance at a location where no cell vertical structure will be present, before the actual gate electrode formation process. This preliminary structure serves as a template or guide that helps establish proper alignment and process parameters, reducing the likelihood of defects in subsequent gate electrode formations
Solution Approach 2:
The patent employs different material compositions for different gate electrode layers - the first gate electrode uses a first material, the second gate electrode uses a second material, and the third gate electrode uses a third material. These parameter changes in material properties allow optimization of each layer for its specific function and reduce defects by selecting materials with appropriate electrical, mechanical, and thermal characteristics for each position in the stack
3Reliability
If dummy vertical structures with buffer regions are introduced to support gate electrodes, then the reliability is improved, but the device complexity increases
Solution Approach 1:
A buffer region is introduced as an intermediary layer between the dummy gate electrode and the cell vertical structure. This buffer region, formed with a specific material composition, acts as a mediator that prevents direct electrical contact between potentially conductive elements, thereby preventing electrical shorts while maintaining structural support. The buffer region is integrated into the existing vertical structure formation process rather than being a separate additive component
Data Source
AI summary
A three-dimensional semiconductor device is provided including a gate electrode disposed on a substrate and having a pad region, a cell vertical structure passing through the gate electrode, a dummy vertical structure passing through the pad region, and a gate contact plug disposed on the pad region. The cell vertical structure includes a cell pad layer disposed on a level higher than that of the gate electrode and a cell channel layer opposing the gate electrode, the dummy vertical structure includes a buffer region formed of a material different from that of the cell pad layer and a dummy channel layer formed of a material the same as that of the cell channel layer, and at least a portion of the buffer region is located on the same plane as at least a portion of the cell pad layer.