Semiconductor Device Vertical Gate Pad Layout for Conduction Resistance
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Solution Overview
Problem
Conventional semiconductor devices face challenges in reducing conduction resistance in current channels on mounting substrates, which affects their performance in applications requiring efficient current flow and low power consumption.
Innovation Solution
A chip-size-package-type semiconductor device with a facedown mountable design, featuring two vertical metal oxide semiconductor (MOS) transistors and a common drain region, where the transistors are aligned in the direction of principal current flow, and the gate pads are strategically positioned to minimize obstacles in the current channel, reducing conduction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the current channel is designed to carry large current through the mounting substrate, then the conduction resistance should be lowered, but the gate pad positioning becomes more complex and restrictive
Solution Approach 1:
The patent transitions from conventional horizontal pad arrangement to a vertical arrangement where gate pads are positioned above source pads in the vertical direction. This dimensional change allows current channels to flow vertically through the substrate without being blocked by horizontally positioned gate pads, thereby reducing conduction resistance while maintaining manageable pad positioning complexity.
Solution Approach 2:
The mounting substrate is divided into multiple current channels with distinct source and drain regions. By segmenting the substrate into separate conduction paths and positioning gate pads vertically above specific source pads, the design enables independent current flow paths that minimize interference and reduce overall conduction resistance.
2Loss of energy
If vertical MOS transistors are aligned in the direction of principal current flow, then conduction resistance is reduced, but the gate pads occupy more space in the current channel path
Solution Approach 1:
Gate pads are positioned in the vertical dimension above source pads rather than extending horizontally into the current channel path. This vertical stacking arrangement allows the gate pads to control the transistors effectively while occupying minimal space in the horizontal current flow direction, thus reducing conduction resistance without sacrificing gate control functionality.
3Loss of energy
If source pads are positioned away from the gate pad to avoid obstruction, then conduction resistance is reduced, but the transistor layout becomes more restrictive
Solution Approach 1:
The patent establishes a vertical stacking arrangement where gate pads are positioned above source pads in the vertical dimension rather than requiring horizontal separation. This dimensional reorganization maintains adequate spacing to minimize conduction resistance while providing a standardized, flexible layout pattern that can be adapted to various transistor configurations and current channel designs.
Data Source
AI summary
A semiconductor device includes a first transistor disposed in a first region of a semiconductor layer and a second transistor disposed in a second region of the semiconductor layer, and includes, on the surface of the semiconductor layer, first source pads, a first gate pad, second source pads, and a second gate pad. In the plan view of the semiconductor layer, the first and second transistors are aligned in a first direction; the first gate pad is disposed such that none of the first source pads is disposed between the first gate pad and a side parallel to the first direction and located closest to the first gate pad; and the second gate pad is disposed such that none of the second source pads is disposed between the second gate pad and a side parallel to the first direction and located closest to the second gate pad.