Semiconductor Device With Vertical Gate Structure
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current DRAM units with buried gate structures face limitations in fabrication capability, affecting performance and reliability as electronic products trend towards miniaturization and higher integration.
Innovation Solution
The implementation of a semiconductor device with a shallow trench isolation (STI) and a gate structure comprising horizontal and vertical portions, along with spacers on sidewalls, to enhance the connection between memory and active regions without metal interconnections, allowing for improved signal transmission and reduced pitch of metal interconnections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional DRAM units with planar gate structures are used, then fabrication is simpler, but carrier channel length is shorter leading to increased capacitor leakage
Solution Approach 1:
The gate structure is segmented into multiple portions (first gate portion, second gate portion, third gate portion) with different configurations. The first and second gate portions have different widths, and the third gate portion has a different width again, allowing each segment to be optimized for specific functions while maintaining overall fabrication feasibility
Solution Approach 2:
The gate structure transitions from a conventional planar two-dimensional configuration to a three-dimensional structure with vertical portions extending into the substrate and horizontal portions at different levels, increasing the effective channel length without proportionally increasing the footprint area
2Reliability
If metal interconnections are used to connect transistors between memory and active regions, then connection is straightforward, but pitch increases and signal transmission efficiency decreases
Solution Approach 1:
The gate structure merges the functions of separate interconnections by having the third gate portion directly connect to doped regions in the substrate, eliminating the need for separate metal interconnection layers for this specific connection path
Solution Approach 2:
Doped regions in the substrate serve as intermediary connection elements between the third gate portion and the active region, replacing direct metal interconnections and enabling more efficient signal transmission through the substrate itself
Data Source
AI summary
A semiconductor device includes a shallow trench isolation (STI) in a substrate and a first gate structure on the STI. Preferably, the first gate structure comprises a first horizontal portion on the STI, a vertical portion connected to the first horizontal portion and extended into part of the STI, and a second horizontal portion connected to the vertical portion. The semiconductor device further includes a first spacer on a sidewall of the first gate structure and the STI and a second spacer on another sidewall of the first gate structure and on the second horizontal portion.