Semiconductor Package Vertical Routing for Noise Reduction
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Solution Overview
Problem
In semiconductor packaging, the limitations on conductive wire length in chip scale packages (CSPs) such as bump chip carriers (BCC) and thin substrate chip scale packages (TSCSPs) lead to increased noise signals and prolonged wire bonding processes, hindering the development of high-speed, high-performance, and reliable electronic products.
Innovation Solution
A semiconductor package design featuring an insulative layer with conductive patterns and metal pad layers, where the conductive patterns are formed with multiple metal layers and an encapsulant is used to reduce wire length, enabling efficient routing and noise reduction through normal wire bonding.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-generated harmful factors
If the length of electrically conductive wire is reduced to reduce noise signal, then noise signal is reduced, but wire bonding process time is prolonged due to limitations in bonding method
Solution Approach 1:
The patent transitions from planar wire routing to three-dimensional vertical routing by forming conductive patterns through the substrate thickness. This allows wires to connect directly between upper and lower surfaces, reducing wire length and noise while enabling faster bonding processes through the novel channel structure
Solution Approach 2:
The patent introduces an encapsulant material as an intermediary that fills channels formed in the insulative layer. This encapsulant serves as both a structural support for the conductive patterns and a medium that enables direct vertical wire routing, resolving the conflict between wire length reduction and bonding process efficiency
2Volume of moving object
If chip scale package (CSP) technology is used to make products thin and small, then product size is reduced, but conductive wire length is limited causing increased noise
Solution Approach 1:
The patent utilizes the vertical dimension through substrate thickness to route conductive patterns, allowing direct connections between upper and lower surfaces. This three-dimensional routing approach reduces wire length and noise while maintaining the compact CSP form factor
Solution Approach 2:
The patent embeds conductive patterns within channels formed in the insulative layer, nesting the wiring structure inside the substrate itself. This nested configuration minimizes external wire length and noise while preserving the compact package design
3Length of stationary object
If TSCSP is used to achieve thin substrate design, then substrate thickness is reduced, but wire routing is limited due to board mounting constraints
Solution Approach 1:
The patent exploits the vertical dimension by forming conductive patterns that extend through the substrate thickness in channels. This vertical routing approach bypasses traditional planar routing limitations and enables effective wire connections in thin substrate designs
Solution Approach 2:
The patent segments the substrate into distinct functional layers including insulative layers with channels, conductive patterns, and encapsulant regions. This segmentation allows independent optimization of each layer for thin substrate design while maintaining wire routing capability
Data Source
AI summary
A semiconductor package has an insulative layer having at least one channel formed on a first surface thereof. A conductive pattern conforming to the at least one channel and exposed to a bottom surface of the semiconductor package is formed. A semiconductor die is electrically connected to the conductive patterns. An encapsulant is used to at least partially filling the at least one channel.