3D Semiconductor Device Vertical Pillar Bit Line Contact
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Solution Overview
Problem
Current three-dimensional semiconductor devices face challenges in efficiently connecting bit lines to vertical pillars due to differences in pattern density between the cell array and connection regions, leading to potential failures such as dishing during the fabrication process.
Innovation Solution
The semiconductor device incorporates a grid structure of cell and peripheral dummy lines in the interlayer dielectric layer, which minimizes the occurrence of failures by eliminating the need for subsidiary lines to connect bit line lower contacts, and directly connects vertical pillars to bit lines through bit line contact structures, thereby reducing pattern density-related issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If subsidiary lines are used to connect bit line lower contacts in conventional three-dimensional semiconductor devices, then connectivity is achieved, but pattern density differences between cell array and connection regions cause dishing failures and reduced reliability
Solution Approach 1:
The patent removes subsidiary lines from the device structure entirely. Instead of using additional connecting lines to bridge bit line lower contacts, the design directly connects vertical pillars to bit lines through bit line contact structures, eliminating the source of pattern density-related dishing failures
Solution Approach 2:
The patent transitions from a two-dimensional planar connection approach to a three-dimensional vertical connection approach. Bit line contact structures extend vertically to directly connect bit lines to vertical pillars, eliminating the need for subsidiary lines that caused manufacturing issues in conventional planar designs
2Ease of manufacture
If conventional connection methods are used, then device structure is simpler, but dishing failures occur during fabrication due to pattern density differences
Solution Approach 1:
The patent introduces bit line contact structures as intermediary elements that directly connect vertical pillars to bit lines. These contact structures serve as the sole connection path, eliminating the need for subsidiary lines and preventing dishing failures while maintaining manufacturing simplicity
Data Source
AI summary
A semiconductor device comprises a plurality of stack structures that include gate electrodes sequentially stacked on a substrate and are disposed along a first direction, and a plurality of separating insulation layers each of which is disposed between the stack structures. A plurality of vertical pillars penetrate each of the stack structures and are connected to the substrate. A plurality of bit lines are disposed on the vertical pillars and run across the stack structures in the first direction. A plurality of bit line contact structures connect the vertical pillars to the bit lines. A plurality of first cell dummy lines are disposed on the plurality of separating insulation layers and extend in a second direction crossing the first direction.