3D Semiconductor Device Vertical Stacking Fabrication
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Solution Overview
Problem
The challenge in increasing integration in two-dimensional semiconductor devices is limited by the need for expensive process equipment to achieve finer patterns, which restricts the potential for higher integration and performance while maintaining cost-effectiveness.
Innovation Solution
A three-dimensional semiconductor device is developed with a structure that includes a lower insulating layer, an electrode structure with conductive patterns, and a vertical insulating layer, allowing for uniform horizontal distances between semiconductor and conductive patterns, and using a method that involves forming a layer stack with sacrificial layers and interlayer dielectrics to create recess regions for conductive pattern formation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two-dimensional or planar semiconductor memory devices are used, then manufacturing process is simpler, but integration is limited due to area constraints and expensive process equipment requirements for finer patterns
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor memory devices to three-dimensional vertical structures. The memory device includes vertically stacked conductive patterns (word lines, bit lines, source lines) and semiconductor patterns extending in the vertical direction, enabling increased integration without requiring finer lateral patterning. This dimensional change allows achieving higher density while avoiding the need for expensive fine-patterning equipment.
2Manufacturing precision
If pattern fineness is increased to achieve higher integration, then integration density improves, but expensive process equipment is required
Solution Approach 1:
By stacking conductive patterns and semiconductor patterns vertically, the patent achieves high integration density through the third dimension rather than through lateral pattern refinement. The vertical stacking of word lines, bit lines, and source lines creates a three-dimensional memory structure that increases capacity without requiring advanced fine-patterning processes, thereby avoiding expensive equipment requirements.
Solution Approach 2:
The patent employs sacrificial layers (first sacrificial layer and second sacrificial layers) that are formed in advance to define the positions and shapes of the vertical patterns. These sacrificial layers are removed selectively to create recess regions where conductive patterns are subsequently formed. This preliminary structuring simplifies the final patterning steps and reduces the need for complex fine-patterning equipment.
3Manufacturing precision
If vertical stacking of conductive patterns is implemented, then integration increases, but manufacturing complexity increases
Solution Approach 1:
Sacrificial layers are formed in advance to pre-define the three-dimensional structure. The first sacrificial layer is formed on the substrate, followed by alternating stacks of interlayer dielectrics and second sacrificial layers. Trenches are then etched through this stack to expose the sacrificial layers, which are subsequently selectively removed to create the vertical recess regions. This preliminary structuring simplifies the formation of complex vertical patterns.
Solution Approach 2:
Sacrificial layers serve as intermediary structures that facilitate the formation of vertical conductive patterns. These temporary structures are used to define the geometry and positioning of the final conductive patterns (word lines, bit lines, source lines) and are removed after serving their structural guidance function. The sacrificial layers act as mediators that simplify the creation of complex three-dimensional architectures.
4Manufacturing precision
If selective removal of sacrificial layers is performed, then recess regions are formed for conductive patterns, but process steps increase
Solution Approach 1:
Different sacrificial layers are removed selectively based on their local positions and functions. The first sacrificial layer is removed to form lower recess regions, while the second sacrificial layers are removed to form upper recess regions. This selective local removal creates precisely defined recess regions at different heights and positions, enabling accurate placement of conductive patterns without requiring a single complex removal process.
Solution Approach 2:
The patent employs different etch selectivities for removing different sacrificial layers. The first sacrificial layer has a different etch selectivity compared to the second sacrificial layers, allowing selective removal through appropriate etching conditions. This parameter-based differentiation enables efficient and precise formation of recess regions at different stages of the fabrication process.
Data Source
AI summary
A three-dimensional semiconductor device and a method of fabricating the same, the device including a lower insulating layer on a top surface of a substrate; an electrode structure sequentially stacked on the lower insulating layer, the electrode structure including conductive patterns; a semiconductor pattern penetrating the electrode structure and the lower insulating layer and being connected to the substrate; and a vertical insulating layer interposed between the semiconductor pattern and the electrode structure, the vertical insulating layer crossing the conductive patterns in a vertical direction and being in contact with a top surface of the lower insulating layer.