Semiconductor Device Vertical Stacking Segmentation
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Solution Overview
Problem
The manufacturing process of three-dimensional semiconductor memory devices is complex and requires innovative solutions to simplify the integration of memory cells and reduce manufacturing difficulties.
Innovation Solution
A semiconductor device design featuring a first stack structure with alternately stacked interlayer insulating layers and conductive patterns, along with a second conductive pattern that includes electrode portions and a connecting portion, allows for a vertical channel and vertical conductive structure that pass through the stack structure, reducing manufacturing complexity by separating conductive patterns and using a separation insulating layer to enhance integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in three dimensions on a substrate to improve integration density, then integration density is improved, but manufacturing complexity increases
Solution Approach 1:
The conductive patterns are segmented into separate stacks (first conductive patterns in a first stack structure, second conductive patterns in a second stack structure) that are formed independently and then integrated. This segmentation allows each stack to be manufactured separately with simplified processes, reducing overall manufacturing complexity while maintaining high integration density through vertical stacking.
Solution Approach 2:
The patent transitions from planar two-dimensional arrangement to three-dimensional vertical stacking of memory cells and conductive patterns. By utilizing the vertical dimension with multiple stacked layers of conductive patterns and interlayer insulating layers, the integration density is significantly improved while the manufacturing process is simplified through the separated stack formation approach.
2Reliability
If conductive patterns are integrated in a single stack structure, then device functionality is achieved, but manufacturing difficulty increases
Solution Approach 1:
The conductive patterns are divided into two separate stacks (first and second stack structures) that can be manufactured independently using different manufacturing processes or at different stages. This segmentation reduces the difficulty of forming complex conductive patterns in a single integrated structure, as each stack can be optimized and formed separately before being combined.
Solution Approach 2:
Interlayer insulating layers serve as intermediary elements between the first and second conductive patterns, enabling the separation of manufacturing processes. These insulating layers allow independent formation of each conductive pattern stack while maintaining electrical isolation and structural integrity, thus reducing manufacturing difficulty without compromising device functionality.
Data Source
AI summary
A semiconductor device includes a first stack structure including first interlayer insulating layers and first conductive patterns alternately stacked on each other in a first direction and a second conductive pattern comprising electrode portions and a connecting portion. The electrode portions of the second conductive pattern are stacked to be spaced apart from each other above the first stack structure. The connecting portion of the second conductive pattern extends in the first direction to intersect the electrode portions and couples the electrode portions. The semiconductor device further includes a vertical channel and a vertical conductive structure that pass through the first stack structure and the electrode portions of the second conductive pattern. The vertical conductive structure is spaced apart from the first stack structure and the second conductive pattern.