Semiconductor Via Alignment Prevents Seed Layer Delamination

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Solution Overview

Problem

In semiconductor packaging, the integration of smaller components requires innovative techniques to prevent delamination of seed layers during the formation of vias, as excessive copper diffusion from conductive features can lead to delamination and reliability issues.

Innovation Solution

A method involving the formation of redistribution structures with specific via configurations and conductive connectors, where the second via is longer than the first via, and conductive connectors are aligned with the second via to avoid copper diffusion from the second and third conductive features, ensuring that the intermetallic compound forms within the via rather than laterally, thus preventing delamination.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conductive connectors are aligned with conductive features during reflow, then intermetallic compound forms at the interface, but copper diffuses laterally from conductive features causing seed layer delamination

Engineering Contradiction:
Improvebonding reliabilityVSAvoidcopper diffusion
Core Design Contradiction:
ReliabilityVSObject-generated harmful factors

Solution Approach 1:

The patent introduces an intermediary structure (the via structure with specific geometry and positioning) between the conductive connector and the conductive feature. This intermediary via structure controls the diffusion path of copper, allowing intermetallic compound formation for bonding while preventing harmful lateral diffusion from the conductive feature, thus resolving the contradiction between bonding reliability and copper diffusion control.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If minimum feature size is reduced to increase integration density, then more components fit in given area, but packaging becomes more difficult and reliability decreases

Engineering Contradiction:
Improveintegration densityVSAvoidpackage reliability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent transitions from two-dimensional planar packaging to three-dimensional vertical packaging by stacking multiple semiconductor packages vertically. This dimensional change allows high integration density while maintaining larger feature sizes and improved packaging reliability, as each package in the stack can be independently optimized for reliability while achieving overall high density through vertical stacking.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces copper diffusion from the conductive features, preventing delamination of seed layers and enhancing the reliability of semiconductor packages by controlling the formation of the intermetallic compound within the vias.

Implementation Method 1

copper is diffused from the second via, and not from the second and third conductive features

Methodology Applied
Scientific EffectDiffusion: Diffusion

Data Source

PatentUS11682655B2Semiconductor packages and methods of forming the same
Publication Date: 2023.06.20 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US11682655B2 patent drawing
  • US11682655B2 patent drawing
  • US11682655B2 patent drawing

AI summary

A method includes forming a first redistribution structure by depositing a first dielectric layer and forming first and second conductive features on the first dielectric layer, the second conductive feature being provided with a gap exposing the first dielectric layer. The method further includes depositing a second dielectric layer on the first and second conductive features; forming first and second openings in the second dielectric layer, the first opening exposing the first conductive feature and the second opening exposing the second conductive feature and the gap; forming a first via on the first conductive feature and partially in the first opening; forming a second via on the second conductive feature and partially in the second opening and the gap; attaching a die to the first redistribution structure adjacent the first via and the second via; and encapsulating the die, the first via, and the second via with an encapsulant.