Semiconductor Via Bottom Pattern for Lower Resistance and Heat Dissipation
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Solution Overview
Problem
Existing semiconductor devices face challenges in heat dissipation and series resistance due to dielectric residue in via structures, which affect performance in high-power applications.
Innovation Solution
The design of conductive vias with specific geometric patterns and non-overlapping centers in the bottom pattern, minimizing dielectric residue and optimizing via trench filling to reduce series resistance and enhance heat dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional via structures are used in semiconductor devices, then manufacturing is simpler, but dielectric residue accumulates in via structures increasing series resistance and reducing heat dissipation
Solution Approach 1:
The via structure is segmented into multiple sections with varying cross-sectional areas. The via includes a first section with a first cross-sectional area and a second section with a second cross-sectional area that is larger than the first. This segmentation allows the via to taper or expand in specific regions, preventing dielectric residue accumulation while maintaining manufacturing feasibility through controlled geometry changes.
Solution Approach 2:
The via structure transitions from a uniform two-dimensional cross-section to a three-dimensional tapered or expanded structure. By introducing dimensional variation along the via height, the patent creates expanded regions that facilitate complete etching and filling processes, eliminating dielectric residue that would accumulate in straight cylindrical via structures.
2Loss of energy
If via cross-sectional area is increased to reduce series resistance, then heat dissipation improves, but dielectric residue accumulation increases
Solution Approach 1:
The via is divided into sections with different cross-sectional areas optimized for different functions. The narrower first section provides good etch access and filling control, while the expanded second section reduces series resistance and improves heat dissipation. The segmentation strategy allows each section to be optimized without compromising the other, preventing dielectric residue while minimizing resistance.
Solution Approach 2:
Different sections of the via have different cross-sectional areas tailored to local requirements. The expanded second section is strategically positioned where lower resistance and improved heat dissipation are most beneficial, while the first section maintains dimensions suitable for precise manufacturing and complete filling, eliminating dielectric residue locally in each region.
3Temperature
If via geometry is optimized for heat dissipation, then thermal performance improves, but manufacturing complexity increases
Solution Approach 1:
The via geometry is segmented into discrete sections with defined cross-sectional areas rather than using complex continuous variations. This segmentation allows standard semiconductor manufacturing processes to create the tapered or expanded structure through controlled etching and filling steps, reducing manufacturing complexity while achieving the thermal performance benefits of increased cross-sectional area for heat dissipation.
Data Source
AI summary
The present disclosure provides a semiconductor substrate, including a first dielectric layer with a first surface and a second surface, a first conductive via extending between the first surface and the second surface, a first patterned conductive layer on the first surface, and a second patterned conductive layer on the second surface. The first conductive via includes a bottom pattern on the first surface and a second patterned conductive layer on the second surface. The bottom pattern has at least two geometric centers corresponding to at least two geometric patterns, respectively, and a distance between one geometric center and an intersection of the two geometrical patterns is a geometric radius. A distance between the at least two geometric centers is greater than 1.4 times the geometric radius. A method for manufacturing the semiconductor substrate described herein and a semiconductor package structure having the semiconductor substrate are also provided.