Semiconductor Package Via Contact Routing
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Solution Overview
Problem
Existing leadframe-based semiconductor packages face limitations in trace routing density and reliability, particularly for high-frequency applications, with a need for thinner profiles, higher I/O counts, and improved electrical performance at lower costs.
Innovation Solution
A semiconductor package design featuring a base substrate with via contacts and a conductive layer having openings that match the conductive trace layout, allowing direct coupling of conductive traces to via contacts, along with an encapsulating cap to enhance electrical conductivity and reliability, while maintaining a low manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If leadframe-based packages are used, then I/O devices can be packaged, but trace routing density is limited
Solution Approach 1:
The patent transitions from traditional planar leadframe routing to a three-dimensional stacked package architecture. Multiple semiconductor dies are vertically stacked and interconnected through through-silicon vias (TSVs), enabling signal routing in the vertical dimension. This dimensional change dramatically increases the effective trace routing density without proportionally increasing package footprint or structural complexity.
Solution Approach 2:
The patent implements a nested architecture where multiple semiconductor dies are stacked vertically within a single package footprint. Each die contains functional circuits, and the stack is interconnected through TSVs that pass through intermediate die layers. This nesting approach multiplies the effective routing capacity within the same physical envelope, achieving high trace routing density without linearly increasing package complexity.
2Reliability
If leadframe-based packages are used, then packaging is achieved, but package level reliability is limited
Solution Approach 1:
The patent incorporates preliminary reliability-enhancing features into the manufacturing process. Through-silicon vias are formed and filled with conductive material before die stacking, creating pre-established reliable interconnect pathways. The package substrate is pre-configured with TSVs and conductive traces that align with die pads, ensuring reliable electrical connections are established before final assembly. This preliminary structuring of interconnects significantly improves package-level reliability.
Solution Approach 2:
The patent employs composite material structures to enhance reliability. The package substrate integrates silicon-based TSVs with copper or other conductive fill materials, combined with dielectric layers and solder bumps. This composite construction provides mechanical strength, electrical conductivity, and thermal management capabilities, collectively improving package reliability while maintaining manufacturability through established semiconductor fabrication processes.
3Quantity of substance
If HLA packages are used for high frequency applications, then I/O count is increased, but electrical performance efficiency is reduced
Solution Approach 1:
The patent utilizes vertical stacking to achieve high I/O counts without the electrical performance degradation associated with dense planar routing. By moving interconnects into the vertical dimension through TSVs, signal paths are shortened and impedance control is improved. The vertical architecture enables numerous I/O connections while maintaining excellent electrical performance for high-frequency applications, as signals travel through optimized three-dimensional pathways rather than congested two-dimensional traces.
4Quantity of substance
If improved signal routing density is achieved, then electrical performance is enhanced, but package profile thickness increases
Solution Approach 1:
The patent employs thin-film deposition techniques to create the conductive layers, dielectric films, and TSV liner materials. These thin-film structures provide the necessary electrical and mechanical functions with minimal thickness. The package substrate and encapsulation layers are designed as thin, optimized structures that protect the stacked dies while maintaining a compact overall profile. This thin-film approach enables high signal routing density without proportionally increasing package thickness.
Data Source
AI summary
Package substrate, semiconductor packages and methods for forming a semiconductor package are presented. The package substrate includes a base substrate having first and second major surfaces and a plurality of via contacts extending through the first to the second major surfaces of the base substrate. A first conductive layer having a plurality of openings is disposed over the first surface of the base substrate and via contacts. The openings are configured to match conductive trace layout of the package substrate. Conductive traces are disposed over the first conductive layer. The conductive traces are directly coupled to the via contacts through some of the openings of the first conductive layer.