Semiconductor Via Structure Layout for Contact Resistance Stability
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Solution Overview
Problem
As semiconductor integration density increases, existing via structures face challenges in maintaining physical and electrical reliability, leading to increased electrical resistance and potential damage to integrated circuits due to variations in contact resistance.
Innovation Solution
The semiconductor device incorporates via structures with different widths and heights, where the power via has a larger width and lower bottom surface level than the signal via, optimized for reduced electrical resistance and enhanced reliability, with insulating and barrier patterns to manage contact resistance and prevent integrated circuit damage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If via structures with uniform width and depth are used, then manufacturing is simplified, but electrical resistance increases and reliability deteriorates
Solution Approach 1:
The patent applies local quality by creating via structures with different widths and depths based on their specific functional requirements. Power vias have larger widths and greater depths compared to signal vias, optimizing each type for its particular electrical and mechanical demands rather than using a uniform via design throughout the substrate.
Solution Approach 2:
The via structure is segmented into multiple components including insulating patterns, barrier patterns, and conductive fill patterns. This segmentation allows each component to be independently optimized and manufactured, with the insulating pattern providing electrical isolation and the barrier pattern preventing diffusion, thereby improving overall reliability.
2Reliability
If via bottom surfaces are at the same level, then manufacturing alignment is easier, but contact resistance variations increase
Solution Approach 1:
Different via structures are designed with different bottom surface levels according to their specific contact requirements. Power vias extend deeper into the substrate to reach lower contact regions, while signal vias have shallower depths, allowing each via type to achieve optimal contact resistance for its function.
3Productivity
If via width is reduced to increase integration density, then more vias can be packed, but electrical resistance increases
Solution Approach 1:
The patent implements local quality by assigning different widths to via structures based on their electrical requirements. Power vias that carry higher currents are designed with larger widths to reduce resistance, while signal vias can have smaller widths. This localized optimization allows high integration density while maintaining low resistance where needed.
Solution Approach 2:
The patent addresses the resistance-d density tradeoff by utilizing the depth dimension. Instead of only varying width, the via structures extend to different depths within the substrate, allowing power vias to reach lower contact regions for better electrical connection while maintaining high integration density through vertical optimization.
Data Source
AI summary
A semiconductor device may include a substrate including a first surface and a second surface, which are opposite to each other, an insulating layer on the first surface of the substrate, a first via structure and a second via structure penetrating the substrate and a portion of the insulating layer and having different widths from each other in a direction parallel to the first surface of the substrate, metal lines provided in the insulating layer, and an integrated circuit provided on the first surface of the substrate. A bottom surface of the first via structure may be located at a level lower than a bottom surface of the second via structure, when measured from the first surface of the substrate. The second via structure may be electrically connected to the integrated circuit through the metal lines.