Semiconductor Via Contact Width Optimization
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Solution Overview
Problem
Current semiconductor devices face challenges in increasing data storage capacity while maintaining electrical properties and reliability, particularly as integration density of three-dimensionally arranged memory cells is enhanced.
Innovation Solution
The semiconductor device incorporates a peripheral circuit structure with multiple wiring layers, via contacts, and a memory stack structure featuring a plate common source line, insulating plug, and lateral insulating spacer, where the width of the via contacts is greater than the insulating plug, facilitating improved electrical connections and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the integration density of memory cells is increased by arranging them three-dimensionally, then the data storage capacity is improved, but the electrical properties and reliability deteriorate
Solution Approach 1:
The device is divided into distinct functional regions: a peripheral circuit structure containing circuits and wiring layers, and a memory stack structure containing memory cells. These structures are separated by a plate common source line and lateral insulating spacers, allowing independent optimization of each region while maintaining overall reliability despite high integration density
Solution Approach 2:
Memory cells are arranged three-dimensionally in a vertical stack structure rather than two-dimensionally on a single plane. Multiple gate lines are stacked vertically with through contacts connecting to via contacts in the peripheral circuit, enabling high storage capacity while maintaining electrical performance through vertical integration
2Reliability
If the width of via contacts is increased to improve connection reliability, then the manufacturing precision requirements are relaxed, but the device complexity increases
Solution Approach 1:
The via contacts have a width that is intentionally designed to be greater than the insulating plug width, creating a localized overlapping region. This local geometric feature ensures that even with manufacturing variations, the via contacts maintain reliable electrical connection to the peripheral circuit wiring layers without requiring excessive precision across the entire device
Data Source
AI summary
A semiconductor device includes a peripheral circuit structure including circuits, wiring layers, and via contacts, a plate common source line covering the peripheral circuit structure, an insulating plug passing through the plate common source line, a lateral insulating spacer between the peripheral circuit structure and the plate common source line, a memory stack structure including gate lines on the plate common source line, a through contact passing through at least one of the gate lines and the insulating plug, the through contact being connected to a first via contact of the via contacts, and a source line contact passing through the lateral insulating spacer, the source line contact being between a second via contact of the via contacts and the plate common source line, wherein a width of the first via contact is greater than a width of the insulating plug in a lateral direction.