Semiconductor Via Structure With Multi-Layer Etch Stop Alignment
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor integrated circuits (ICs) lead to challenges in forming conductive vias aligned with underlying conductive features, resulting in reduced contact area and increased overlay shift problems.
Innovation Solution
The use of multiple etch stop layers, including a first etch stop layer formed over a dielectric layer using atomic layer deposition, and a capping layer, helps to align conductive vias with underlying conductive features, increasing contact area and reducing overlay shift issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If multiple etch stop layers are added to improve via alignment, then manufacturing precision improves, but device complexity increases
Solution Approach 1:
The patent divides the etch stop function into multiple separate layers (first etch stop layer, second etch stop layer, third etch stop layer) with different materials and etch selectivities. Each layer independently provides alignment reference for specific via types, enabling precise control of via positions without requiring complex single-layer solutions or post-forming adjustments.
Solution Approach 2:
The etch stop layers serve as intermediary reference structures between the conductive features and the via formation process. These layers provide distinct etch selectivity interfaces that mediate the alignment process, allowing different via types to be precisely positioned relative to their corresponding conductive features through selective etching processes.
2Productivity
If feature size is decreased to increase functional density, then productivity improves, but manufacturing precision deteriorates
Solution Approach 1:
The patent applies different materials and etch selectivity characteristics to different etch stop layers, creating local quality variations that enable precise alignment for specific via types. Each etch stop layer is optimized with particular material properties (e.g., silicon nitride, silicon oxide, tantalum oxide) to provide distinct etch resistance profiles, allowing differential control during the via formation process despite miniaturization.
Solution Approach 2:
The etch stop layers are formed in advance before via formation, establishing precise alignment references beforehand. The multiple layers are deposited and patterned prior to via etching, creating pre-positioned reference structures that guide subsequent via formation processes, thereby ensuring accurate via alignment even at reduced feature sizes.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The implementation of multiple etch stop layers enhances the alignment of conductive vias with underlying features, thereby increasing contact area and improving the performance of semiconductor structures by reducing overlay shift problems and enhancing reliability.
Implementation Method 1
a first etch stop layer formed over a dielectric layer using atomic layer deposition
Data Source
AI summary
A semiconductor structure includes a first dielectric layer, a first conductive feature, a second conductive feature, a first etch stop layer, and a conductive via. The first conductive feature and the second conductive feature are embedded in the first dielectric layer. The first etch stop layer is disposed over the dielectric layer. The conductive via is surrounded by the first etch stop layer and electrically connected to the first conductive feature, in which the conductive via is in contact with a top surface of the first etch stop layer.