Semiconductor Via Fabrication with Etch Stop Protection
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Solution Overview
Problem
The conventional dual damascene process for fabricating semiconductor devices is prone to damaging metal layers during trench formation due to uncontrolled etching, necessitating an additional gap fill plug process that increases cost and time.
Innovation Solution
A method involving the formation of first and second partial vias separated by dielectric layers and etch stop pads, respectively, to protect underlying metal and top plates during etching, thereby eliminating the need for a gap fill plug process and reducing costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an etching process for forming the trench is not well-controlled, then the metal layer below the via may be damaged, but if a gap fill plug process is used to protect the metal layer, then the cost and time will increase
Solution Approach 1:
The patent applies preliminary action by forming the first dielectric layer between the bottom metal and the via bottom, and the etch stop pad on the top plate, before the trench etching process. These protective layers are prepared in advance to prevent damage during subsequent etching, eliminating the need for additional gap fill plug processes.
Solution Approach 2:
The patent uses intermediary layers (first dielectric layer and etch stop pad) that act as mediators between the etching process and the metal layers. These intermediary protective layers absorb the etching damage that would otherwise affect the bottom metal and top plate, allowing direct trench formation without additional protection steps.
2Manufacturing precision
If the etching process is not well-controlled, then the metal layer below the via may be damaged, but if no protection is provided, then the manufacturing precision will be poor
Solution Approach 1:
The patent applies beforehand cushioning by placing the first dielectric layer and etch stop pad in advance to cushion or absorb the harmful effects of uncontrolled etching. These layers serve as sacrificial protective barriers that prevent etching damage to the metal layers while allowing the trench etching process to proceed with standard control.
3Reliability
If a gap fill plug process is used to protect the metal layer during trench formation, then the metal layer is protected, but the fabrication cost and time increase
Solution Approach 1:
The patent merges the protection function into the existing dual damascene process structure by integrating the first dielectric layer and etch stop pad formation into the standard process flow. This combines the protection function with the existing via and trench formation steps, eliminating the need for separate gap fill plug processes and maintaining high fabrication efficiency.
Data Source
AI summary
A method for fabricating a semiconductor device comprises: providing a substrate having a top surface; forming a bottom metal embedded in the substrate; forming a first etch stop layer, a first dielectric layer, a second etch stop layer and a second dielectric layer sequentially stacked on the top surface of the substrate; forming a semiconductor element disposed on the first etch stop layer, wherein the semiconductor element comprises a top plate and an etch stop pad disposed on the top plate; performing a first etching process to form a first partial via and a second partial via penetrating the second dielectric layer, the second etch stop layer and a portion of the first dielectric layer, wherein the first partial via is separated from the bottom metal by the first dielectric layer, and the second partial via is separated from the top plate by the etch stop pad.