Semiconductor Via Etching Using Isolation Stops for Dense Transistor Layouts
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Solution Overview
Problem
Existing semiconductor manufacturing methods face challenges in controlling the etching rate difference of via openings with different widths, leading to potential interference with transistors and limiting the density of transistor arrangements.
Innovation Solution
A method is employed to control the etching rate difference by using an isolation structure as an etch stop layer for wider via openings, and through multiple etching processes with passivation layers to form vias with varying widths, ensuring minimal interference with transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a single etching process is used to form via openings of different widths, then the manufacturing process is simple, but the etching time differences are large and transistor interference occurs
Solution Approach 1:
The etching process is divided into multiple sequential etching processes, where each process targets specific via openings based on their width characteristics. Narrow via openings are etched in earlier processes while wider via openings are etched in later processes, allowing precise depth control for each via type without interfering with transistor regions.
Solution Approach 2:
The patent employs periodic etching cycles with alternating etching and non-etching periods. During etching periods, specific via openings are etched based on the current process stage; during non-etching periods, other via openings are protected. This periodic action enables differential etching depth control for via openings of different widths.
2Productivity
If via openings are etched to the same depth, then the etching process is uniform, but wider via openings cause transistor interference and limit transistor density
Solution Approach 1:
Different etching depths are applied to different via openings based on their local characteristics (width and position). Narrow via openings near transistor regions are etched to controlled depths that prevent transistor interference, while wider via openings in peripheral regions are etched deeper. This local quality approach minimizes harmful effects on transistors while maintaining manufacturing efficiency.
3Manufacturing precision
If multiple etching processes are used to control via opening depths, then transistor interference is reduced, but the manufacturing process becomes complex
Solution Approach 1:
The multiple etching processes use the same etching solution and follow a standardized procedural framework, making each etching process multi-functional. The universal process structure handles different via opening types through systematic differentiation rather than requiring entirely separate specialized processes, thereby controlling complexity while achieving precise depth control.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the etching time difference between via openings with different widths, allowing for denser transistor arrangements by minimizing the impact of signal vias on transistors, thereby increasing the number of transistors per area.
Implementation Method 1
A first etching process is performed to form a first via opening and a second via opening in the substrate. A second etching process is performed such that the first via opening extends to a bottom of the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure
Implementation Method 2
forming a passivation layer along sidewalls and a bottom surface of the first via opening, removing the passivation layer at the bottom surface of the first via opening, etching the bottom of the first via opening to deepen the first via opening
Implementation Method 3
forming the first via and the second via includes depositing a conductive material in the first via opening and the second via opening and over the second wafer, and planarizing the second wafer to remove an excess portion of the conductive material
Data Source
AI summary
A method of manufacturing a semiconductor device includes bonding a first wafer with a second wafer. The second wafer includes a substrate, an isolation structure in the substrate, a transistor on the substrate, and a interconnect structure over the second transistor. A first etching process is performed to form a first via opening and a second via opening in the substrate. The second via opening extends to the isolation structure, and the second via opening is deeper than the first via opening. A second etching process is performed such that the first via opening exposes the substrate. A third etching process is performed such that the first via opening and the second via opening exposes the interconnect structure, and the second via opening penetrates the isolation structure. A first via is formed in the first via opening and a second via is formed in the second via opening.