Semiconductor Via Placement Using Forbidden Regions
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Solution Overview
Problem
The challenge in semiconductor integrated circuit (IC) design is the difficulty in fabricating vias between adjacent signal rails in adjacent cells due to their close proximity, which leads to interference and manufacturing complexities, especially when forbidden regions are not properly managed.
Innovation Solution
The introduction of forbidden regions, such as LFZ and GLFZ patterns, in the layout design helps separate vias, preventing them from being placed too close to each other, thereby simplifying the manufacturing process by defining specific guidelines for via placement based on these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If vias are placed in adjacent cells without forbidden regions, then via density increases, but manufacturing difficulty and interference increase
Solution Approach 1:
The patent divides the cell layout into forbidden regions (LFZ and GLFZ) and non-forbidden regions, segmenting the space where vias can be placed. This segmentation allows via density to be increased in permissible areas while maintaining manufacturability by excluding problematic areas through the defined forbidden regions.
Solution Approach 2:
The patent applies different placement rules to different local areas of the cell. Forbidden regions are defined with specific characteristics (adjacent to signal rails, specific distance ranges) where via placement is restricted, while other areas allow via placement. This local differentiation enables optimized via density in permissible zones without compromising manufacturing in restricted zones.
2Quantity of substance
If vias are placed close to signal rails, then via density increases, but interference and manufacturing complexity increase
Solution Approach 1:
The patent preemptively defines forbidden regions adjacent to signal rails before via placement occurs. By establishing LFZ (lower forbidden zone) and GLFZ (upper forbidden zone) at predetermined distances from signal rails, the design prevents via placement that would cause interference, eliminating the harmful effect before it can manifest during manufacturing or operation.
Solution Approach 2:
The forbidden regions act as intermediary zones between vias and signal rails. These regions serve as buffer spaces that prevent direct interaction between vias and signal rails, thereby eliminating interference while still allowing via placement in the remaining non-forbidden areas to maintain density.
3Reliability
If forbidden regions are defined with larger distances from signal rails, then interference is reduced, but via placement flexibility decreases
Solution Approach 1:
The patent defines forbidden regions using specific parameter ranges (distances from signal rails) that balance reliability and flexibility. By setting LFZ at distances of 0.5-2.0 times the via diameter and GLFZ at distances of 1.0-3.0 times the via diameter, the design optimizes the trade-off between preventing interference and maintaining via placement flexibility, allowing adaptation to different via sizes and design requirements.
Data Source
AI summary
A semiconductor device includes a cell. The cell includes an active area, gates, at least one gate via and at least one contact via. The active area includes forbidden regions. The gates are disposed across the active area. The at least one gate via is coupled with one of the gates. The at least one contact via is coupled with at least one conductive segment each corresponding to a source/drain of a transistor. In a layout view, one of the forbidden regions abuts a region of an abutted cell in which at least one of a gate via or a contact via of the abutted cell is disposed. In a layout view, the least one of the at least one gate via or the at least one contact via is arranged within the active area and outside of the forbidden regions. A method is also disclosed herein.